Patents by Inventor Nicholas Jarmany

Nicholas Jarmany has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory controller and memory access method
    Patent number: 9690722
    Abstract: A memory controller (10) for a plurality of banks of memory (55a-55c) is disclosed. The memory controller (10) includes an interface (20) connectable to a bus (60) to communicate with a processor (70). The memory controller (10) redundantly maps the plurality of banks of memory (55a-55c) to a memory space (50) and includes a plurality of memory operators, each of the plurality of memory operators being executable by the memory controller for performing a different function on data in the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c). In response to receipt at the interface (20) of a request from the processor (70) for one of said memory operators, the memory controller (10) is configured to execute, independently of the processor (70), the respective memory operator on the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c).
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: June 27, 2017
    Assignee: QUIXANT PLC
    Inventor: Nicholas Jarmany
  • Memory Controller and Memory Access Method
    Publication number: 20150067216
    Abstract: A memory controller (10) for a plurality of banks of memory (55a-55c) is disclosed. The memory controller (10) includes an interface (20) connectable to a bus (60) to communicate with a processor (70). The memory controller (10) redundantly maps the plurality of banks of memory (55a-55c) to a memory space (50) and includes a plurality of memory operators, each of the plurality of memory operators being executable by the memory controller for performing a different function on data in the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c). In response to receipt at the interface (20) of a request from the processor (70) for one of said memory operators, the memory controller (10) is configured to execute, independently of the processor (70), the respective memory operator on the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c).
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Inventor: Nicholas Jarmany