Patents by Inventor Nicholas John Kepler

Nicholas John Kepler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Resist trim process to define small openings in dielectric layers
    Patent number: 7737021
    Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: June 15, 2010
    Assignee: Globalfoundries Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Paul R. Besser, Jonathan B. Smith, Eric M. Apelgren, Christian Zistl, Jeremy I. Martin, Lie Larry Zhao, Nicholas John Kepler
  • Resist trim process to define small openings in dielectric layers
    Patent number: 6500755
    Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: December 31, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Paul R. Besser, Jonathan B. Smith, Eric M. Apelgren, Christian Zistl, Jeremy I. Martin, Lie Larry Zhao, Nicholas John Kepler
  • Resist trim process to define small openings in dielectric layers
    Publication number: 20020068436
    Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.
    Type: Application
    Filed: December 6, 2000
    Publication date: June 6, 2002
    Inventors: Srikanteswara Dakshina-Murthy, Paul R. Besser, Jonathan B Smith, Eric M. Apelgren, Christian Zistl, Jeremy I. Martin, Lie Larry Zhao, Nicholas John Kepler
  • Memory cell having increased capacitance via a local interconnect to gate capacitor and a method for making such a cell
    Patent number: 5844836
    Abstract: A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. A dielectric material such as silicon dioxide may be deposited between the local interconnect and polysilicon conductive lines. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: December 1, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nicholas John Kepler, Asim A. Selcuk, Richard K. Klein, Craig S. Sander, John C. Holst, Christopher A. Spence, Raymond T. Lee, Stephen C. Horne
  • Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device
    Patent number: 5796651
    Abstract: A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A drive circuit generates a reduced word line voltage to activate the pass transistor during a READ operation. The reduced word line voltage has a magnitude less than the magnitude of the bias voltage used to activate the pull-down transistor.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: August 18, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen C. Horne, Richard K. Klein, Asim A. Selcuk, Nicholas John Kepler, Christopher A. Spence, Raymond T. Lee, John C. Holst