Patents by Inventor Nicholas Joy

Nicholas Joy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230197505
    Abstract: A method for patterning a substrate includes: forming a first photoresist etch mask with an extreme ultraviolet (EUV) lithography process, the first photoresist etch mask including first through openings, the first photoresist etch mask including a metal-based photoresist material; forming a second photoresist etch mask over the first photoresist etch mask, the second photoresist etch mask including second through openings; and forming first openings, through the first and the second photoresist etch masks, in a region of the substrate that vertically overlaps both the first through openings and the second through openings.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Inventors: Katie Lutker-Lee, Angelique Raley, Nicholas Joy
  • Patent number: 11621190
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: April 4, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
  • Patent number: 11450562
    Abstract: A method of metallization includes receiving a substrate having a recess formed therein. The recess has a bottom and sidewalls, and a conformal liner is deposited on the bottom and sidewalls of the recess. The conformal liner is removed from an upper portion of the recess to expose upper sidewalls of the recess while leaving the conformal liner in a lower portion of the recess covering the bottom and lower sidewalls of the recess. Metal is deposited in a lower portion of the recess to form a metallization feature including the conformal liner in the lower portion of the recess and the metal.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 20, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Jodi Grzeskowiak, Nicholas Joy, Jeffrey Smith
  • Patent number: 11322364
    Abstract: In accordance with an embodiment, a method of plasma processing includes etching a refractory metal by flowing oxygen into a plasma processing chamber, intermittently flowing a passivation gas into the plasma processing chamber, and supplying power to sustain a plasma in the plasma processing chamber.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: May 3, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Nicholas Joy, Angelique Raley
  • Publication number: 20210313192
    Abstract: In accordance with an embodiment, a method of plasma processing includes etching a refractory metal by flowing oxygen into a plasma processing chamber, intermittently flowing a passivation gas into the plasma processing chamber, and supplying power to sustain a plasma in the plasma processing chamber.
    Type: Application
    Filed: May 8, 2020
    Publication date: October 7, 2021
    Inventors: Nicholas Joy, Angelique Raley
  • Patent number: 11133194
    Abstract: A method of etching a substrate includes generating plasma comprising a first concentration of an etchant and a second concentration of an inhibitor and etching the substrate by exposing an exposed interface between a first material and a second material to the plasma. The first material includes a lower reactivity to both the etchant and the inhibitor than the second material. The first concentration is less than the second concentration. Etching the substrate includes etching the first material and the second material at the exposed interface to form an etched indentation including an enriched region of the second material, forming a passivation layer at the enriched region using the inhibitor, and etching the first material at the etched indentation. The passivation layer reduces an etch rate of the second material to a reduced rate that is less than an etch rate of the first material.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: September 28, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Sergey Voronin, Christopher Catano, Nicholas Joy, Alok Ranjan, Christopher Talone
  • Publication number: 20210287936
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
  • Patent number: 11024535
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: June 1, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
  • Publication number: 20210118693
    Abstract: A method of plasma processing that includes maintaining a plasma processing chamber between 10° C. to 200° C., flowing oxygen and nitrogen into the plasma processing chamber, where a ratio of a flow rate of the nitrogen to a flow rate of oxygen is between about 1:5 and about 1:1, and etching a ruthenium/osmium layer by sustaining a plasma in the plasma processing chamber.
    Type: Application
    Filed: October 21, 2019
    Publication date: April 22, 2021
    Inventors: Nicholas Joy, Devi Koty, Qingyun Yang, Nathan P. Marchack, Sebastian Ulrich Engelmann
  • Publication number: 20210082750
    Abstract: A method of metallization includes receiving a substrate having a recess formed therein. The recess has a bottom and sidewalls, and a conformal liner is deposited on the bottom and sidewalls of the recess. The conformal liner is removed from an upper portion of the recess to expose upper sidewalls of the recess while leaving the conformal liner in a lower portion of the recess covering the bottom and lower sidewalls of the recess. Metal is deposited in a lower portion of the recess to form a metallization feature including the conformal liner in the lower portion of the recess and the metal.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 18, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Kai-Hung YU, Jodi GRZESKOWIAK, Nicholas JOY, Jeffrey SMITH
  • Patent number: 10903077
    Abstract: Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: January 26, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Yoshida, Christopher Catano, Christopher Talone, Nicholas Joy, Sergey Voronin
  • Patent number: 10861744
    Abstract: A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: December 8, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Ying Trickett, Kai-Hung Yu, Nicholas Joy, Kaoru Maekawa, Robert Clark
  • Publication number: 20200266070
    Abstract: A method of etching a substrate includes generating plasma comprising a first concentration of an etchant and a second concentration of an inhibitor and etching the substrate by exposing an exposed interface between a first material and a second material to the plasma. The first material includes a lower reactivity to both the etchant and the inhibitor than the second material. The first concentration is less than the second concentration. Etching the substrate includes etching the first material and the second material at the exposed interface to form an etched indentation including an enriched region of the second material, forming a passivation layer at the enriched region using the inhibitor, and etching the first material at the etched indentation. The passivation layer reduces an etch rate of the second material to a reduced rate that is less than an etch rate of the first material.
    Type: Application
    Filed: February 20, 2020
    Publication date: August 20, 2020
    Inventors: Sergey Voronin, Christopher Catano, Nicholas Joy, Alok Ranjan, Christopher Talone
  • Patent number: 10734278
    Abstract: A process is provided in which low-k layers are protected from etch damage by the use of a selectively formed protection layer which forms on the low-k layer. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. In one embodiment, the selectively formed protection layer may be formed by a selective deposition process which selectively forms layers on the low-k dielectric but not over the conductor layer. The selectively formed protection layer may then be utilized to protect the low-k layer from a plasma etch that is utilized to recess the conductor. In this manner, a conductor (for example metal) may be recessed in a low-k dielectric layer via a plasma etch process.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 4, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hirokazu Aizawa, Karthikeyan Pillai, Nicholas Joy, Kandabara Tapily
  • Patent number: 10700009
    Abstract: A method is provided for void-free Ru metal filling of features in a substrate. The method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 30, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Nicholas Joy, Eric Chih Fang Liu, David L. O'Meara, David Rosenthal, Masanobu Igeta, Cory Wajda, Gerrit J. Leusink
  • Publication number: 20200118871
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 16, 2020
    Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
  • Patent number: 10580691
    Abstract: A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: March 3, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Soo Doo Chae, Kaoru Maekawa, Jeffrey Smith, Nicholas Joy, Gerrit J. Leusink, Kai-Hung Yu
  • Publication number: 20200027736
    Abstract: Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 23, 2020
    Inventors: Yusuke Yoshida, Christopher Catano, Christopher Talone, Nicholas Joy, Sergey Voronin
  • Publication number: 20190385906
    Abstract: A process is provided in which low-k layers are protected from etch damage by the use of a selectively formed protection layer which forms on the low-k layer. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. In one embodiment, the selectively formed protection layer may be formed by a selective deposition process which selectively forms layers on the low-k dielectric but not over the conductor layer. The selectively formed protection layer may then be utilized to protect the low-k layer from a plasma etch that is utilized to recess the conductor. In this manner, a conductor (for example metal) may be recessed in a low-k dielectric layer via a plasma etch process.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 19, 2019
    Inventors: Hirokazu Aizawa, Karthikeyan Pillai, Nicholas Joy, Kandabara Tapily
  • Publication number: 20190295887
    Abstract: A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 26, 2019
    Inventors: Ying Trickett, Kai-Hung Yu, Nicholas Joy, Kaoru Maekawa, Robert Clark