Patents by Inventor Nicholas Joy
Nicholas Joy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250308897Abstract: A method for protecting metal interconnects includes depositing a first layer having a first electrochemical potential over a substrate, depositing a second layer having a second electrochemical potential over the first layer, where the second electrochemical potential is less than the first electrochemical potential. The method includes creating an opening through the second layer, and extending the opening through the first layer by etching the first layer and the second layer, where at least some of the second layer is deposited over the first layer on sidewalls of the opening.Type: ApplicationFiled: March 28, 2024Publication date: October 2, 2025Inventors: Sophia Rogalskyj, Nicholas Joy, Joshua Baillargeon, Nargess Arabchigavkani
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Publication number: 20250308988Abstract: A method for making a semiconductor device can include providing an intermediate structure comprising a substrate, a metal layer, a graphene layer, and a mask layer, where the metal layer is over the substrate, where the graphene layer is over the metal layer, where the mask layer is over the graphene layer, and where the mask layer and the graphene layer are patterned and etched with recesses opening to a top surface of the metal layer such that sidewalls of the graphene layer are exposed in the recesses, conformally depositing a barrier layer over the intermediate structure such that the barrier layer covers the sidewalls of the graphene layer in the recesses, and anisotropically etching the metal layer via the recesses.Type: ApplicationFiled: March 28, 2024Publication date: October 2, 2025Inventors: Christopher Catano, Na Young Bae, Jeffrey Shearer, Brandon Byrns, Joshua Larose, Nicholas Joy, David L O’Meara
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Patent number: 12417925Abstract: A method for processing a substrate that includes: depositing a filling material over the substrate including a first recess and a second recess, the filling material filling the first recess and the second recess; patterning the filling material such that the first recess is reopened while the second recess remains filled with the filling material; filling the first recess with a conductive material to a first height; etching the filling material selectively to the conductive material to reopen the second recess; filling a remainder of the first recess and the second recess with the conductive material; and performing an etch back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height.Type: GrantFiled: November 28, 2022Date of Patent: September 16, 2025Assignee: Tokyo Electron LimitedInventors: Hirokazu Aizawa, Kai-Hung Yu, Nicholas Joy, Yusuke Yoshida, Kandabara Tapily
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Publication number: 20250259891Abstract: A method of etching a liner formed between a patterned layer and a substrate includes forming a conformal protection layer over the patterned layer and the liner, dry etching the liner to expose the substrate using the patterned layer as an etch mask, and wet etching and removing the conformal protection layer. A mask protection structure may be formed at upper surfaces of the patterned layer before dry etching the liner, before or after forming the conformal protection layer. The conformal protection layer may be formed using an atomic layer deposition process. The patterned layer may include a hardmask and a patterned interconnect layer, such as a patterned ruthenium interconnect layer. The substrate may include silicon. Wet etching and removing the conformal protection layer may be part of a cleaning process. The wet etchant may include hydrofluoric acid (HF).Type: ApplicationFiled: February 14, 2024Publication date: August 14, 2025Inventors: Yen-Tien Lu, Nicholas Joy, Shihsheng Chang
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Patent number: 12334391Abstract: A method for patterning a substrate includes: forming a first photoresist etch mask with an extreme ultraviolet (EUV) lithography process, the first photoresist etch mask including first through openings, the first photoresist etch mask including a metal-based photoresist material; forming a second photoresist etch mask over the first photoresist etch mask, the second photoresist etch mask including second through openings; and forming first openings, through the first and the second photoresist etch masks, in a region of the substrate that vertically overlaps both the first through openings and the second through openings.Type: GrantFiled: December 17, 2021Date of Patent: June 17, 2025Assignee: Tokyo Electron LimitedInventors: Katie Lutker-Lee, Angelique Raley, Nicholas Joy
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Publication number: 20250079174Abstract: A method for processing a substrate includes forming a first hardmask layer over a target layer and a second hardmask layer over the first hardmask layer, and patterning the second hardmask layer. The method further includes forming a tone inversion mask between portions of the patterned second hardmask layer, removing the patterned second hardmask layer, patterning the first hardmask layer using the tone inversion mask as an etching mask, and etching the target layer using the patterned first hardmask layer as another etching mask.Type: ApplicationFiled: September 5, 2023Publication date: March 6, 2025Inventors: Eric Chih-Fang Liu, Sophie Thibaut, Nicholas Joy, Christopher Cole
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Publication number: 20240371655Abstract: A method of processing a substrate that includes: forming a patterned hardmask layer over a conductive layer to be etched, the conductive layer disposed over a substrate; and patterning the conductive layer using the patterned hardmask layer as an etch mask, by performing a cyclic plasma etch process to gradually form a recess in the conductive layer, each cycle of the cyclic plasma etch process including exposing the substrate to a first plasma including a halogen to etch the conductive layer, and exposing the substrate to a second plasma including a silicon-containing precursor to deposit a silicon-containing protective layer over a top surface of the patterned hardmask layer.Type: ApplicationFiled: May 4, 2023Publication date: November 7, 2024Inventors: Yen-Tien Lu, Shihsheng Chang, Nicholas Joy
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Patent number: 12057322Abstract: A method of plasma processing that includes maintaining a plasma processing chamber between 10° C. to 200° C., flowing oxygen and nitrogen into the plasma processing chamber, where a ratio of a flow rate of the nitrogen to a flow rate of oxygen is between about 1:5 and about 1:1, and etching a ruthenium/osmium layer by sustaining a plasma in the plasma processing chamber.Type: GrantFiled: October 21, 2019Date of Patent: August 6, 2024Assignees: Tokyo Electron Limited, International Business Machines CorporationInventors: Nicholas Joy, Devi Koty, Qingyun Yang, Nathan P. Marchack, Sebastian Ulrich Engelmann
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Publication number: 20240178003Abstract: A method for processing a substrate that includes: depositing a filling material over the substrate including a first recess and a second recess, the filling material filling the first recess and the second recess; patterning the filling material such that the first recess is reopened while the second recess remains filled with the filling material; filling the first recess with a conductive material to a first height; etching the filling material selectively to the conductive material to reopen the second recess; filling a remainder of the first recess and the second recess with the conductive material; and performing an etch back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height.Type: ApplicationFiled: November 28, 2022Publication date: May 30, 2024Inventors: Hirokazu Aizawa, Kai-Hung Yu, Nicholas Joy, Yusuke Yoshida, Kandabara Tapily
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Publication number: 20230197505Abstract: A method for patterning a substrate includes: forming a first photoresist etch mask with an extreme ultraviolet (EUV) lithography process, the first photoresist etch mask including first through openings, the first photoresist etch mask including a metal-based photoresist material; forming a second photoresist etch mask over the first photoresist etch mask, the second photoresist etch mask including second through openings; and forming first openings, through the first and the second photoresist etch masks, in a region of the substrate that vertically overlaps both the first through openings and the second through openings.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Inventors: Katie Lutker-Lee, Angelique Raley, Nicholas Joy
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Patent number: 11621190Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.Type: GrantFiled: May 28, 2021Date of Patent: April 4, 2023Assignee: Tokyo Electron LimitedInventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
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Patent number: 11450562Abstract: A method of metallization includes receiving a substrate having a recess formed therein. The recess has a bottom and sidewalls, and a conformal liner is deposited on the bottom and sidewalls of the recess. The conformal liner is removed from an upper portion of the recess to expose upper sidewalls of the recess while leaving the conformal liner in a lower portion of the recess covering the bottom and lower sidewalls of the recess. Metal is deposited in a lower portion of the recess to form a metallization feature including the conformal liner in the lower portion of the recess and the metal.Type: GrantFiled: September 15, 2020Date of Patent: September 20, 2022Assignee: Tokyo Electron LimitedInventors: Kai-Hung Yu, Jodi Grzeskowiak, Nicholas Joy, Jeffrey Smith
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Patent number: 11322364Abstract: In accordance with an embodiment, a method of plasma processing includes etching a refractory metal by flowing oxygen into a plasma processing chamber, intermittently flowing a passivation gas into the plasma processing chamber, and supplying power to sustain a plasma in the plasma processing chamber.Type: GrantFiled: May 8, 2020Date of Patent: May 3, 2022Assignee: Tokyo Electron LimitedInventors: Nicholas Joy, Angelique Raley
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Publication number: 20210313192Abstract: In accordance with an embodiment, a method of plasma processing includes etching a refractory metal by flowing oxygen into a plasma processing chamber, intermittently flowing a passivation gas into the plasma processing chamber, and supplying power to sustain a plasma in the plasma processing chamber.Type: ApplicationFiled: May 8, 2020Publication date: October 7, 2021Inventors: Nicholas Joy, Angelique Raley
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Patent number: 11133194Abstract: A method of etching a substrate includes generating plasma comprising a first concentration of an etchant and a second concentration of an inhibitor and etching the substrate by exposing an exposed interface between a first material and a second material to the plasma. The first material includes a lower reactivity to both the etchant and the inhibitor than the second material. The first concentration is less than the second concentration. Etching the substrate includes etching the first material and the second material at the exposed interface to form an etched indentation including an enriched region of the second material, forming a passivation layer at the enriched region using the inhibitor, and etching the first material at the etched indentation. The passivation layer reduces an etch rate of the second material to a reduced rate that is less than an etch rate of the first material.Type: GrantFiled: February 20, 2020Date of Patent: September 28, 2021Assignee: Tokyo Electron LimitedInventors: Sergey Voronin, Christopher Catano, Nicholas Joy, Alok Ranjan, Christopher Talone
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Publication number: 20210287936Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.Type: ApplicationFiled: May 28, 2021Publication date: September 16, 2021Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
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Patent number: 11024535Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.Type: GrantFiled: October 10, 2019Date of Patent: June 1, 2021Assignee: Tokyo Electron LimitedInventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
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Publication number: 20210118693Abstract: A method of plasma processing that includes maintaining a plasma processing chamber between 10° C. to 200° C., flowing oxygen and nitrogen into the plasma processing chamber, where a ratio of a flow rate of the nitrogen to a flow rate of oxygen is between about 1:5 and about 1:1, and etching a ruthenium/osmium layer by sustaining a plasma in the plasma processing chamber.Type: ApplicationFiled: October 21, 2019Publication date: April 22, 2021Inventors: Nicholas Joy, Devi Koty, Qingyun Yang, Nathan P. Marchack, Sebastian Ulrich Engelmann
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Publication number: 20210082750Abstract: A method of metallization includes receiving a substrate having a recess formed therein. The recess has a bottom and sidewalls, and a conformal liner is deposited on the bottom and sidewalls of the recess. The conformal liner is removed from an upper portion of the recess to expose upper sidewalls of the recess while leaving the conformal liner in a lower portion of the recess covering the bottom and lower sidewalls of the recess. Metal is deposited in a lower portion of the recess to form a metallization feature including the conformal liner in the lower portion of the recess and the metal.Type: ApplicationFiled: September 15, 2020Publication date: March 18, 2021Applicant: Tokyo Electron LimitedInventors: Kai-Hung YU, Jodi GRZESKOWIAK, Nicholas JOY, Jeffrey SMITH
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Patent number: 10903077Abstract: Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.Type: GrantFiled: July 15, 2019Date of Patent: January 26, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Yusuke Yoshida, Christopher Catano, Christopher Talone, Nicholas Joy, Sergey Voronin