Patents by Inventor Nicholas K. Eib
Nicholas K. Eib has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9188848Abstract: The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.Type: GrantFiled: December 20, 2012Date of Patent: November 17, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
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Publication number: 20130107240Abstract: The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.Type: ApplicationFiled: December 20, 2012Publication date: May 2, 2013Applicant: LSI CORPORATIONInventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
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Patent number: 8377633Abstract: The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.Type: GrantFiled: October 5, 2011Date of Patent: February 19, 2013Assignee: LSI CorporationInventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
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Publication number: 20120038896Abstract: The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.Type: ApplicationFiled: October 5, 2011Publication date: February 16, 2012Applicant: LSI CORPORATIONInventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
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Patent number: 8057963Abstract: The present invention provides methods and apparatus for accomplishing a optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.Type: GrantFiled: December 14, 2004Date of Patent: November 15, 2011Assignee: LSI CorporationInventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
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Patent number: 8012873Abstract: A method for annealing a semiconductor device having at least one polysilicon region formed on a substrate, comprises growing dielectric material on the substrate adjacent to the polysilicon region. The method continues by polishing a surface of the dielectric material and by depositing a layer of a semi-transparent material on both the surface of the dielectric material and the surface of the polysilicon region. The method concludes by annealing the semiconductor device.Type: GrantFiled: February 11, 2009Date of Patent: September 6, 2011Assignee: SuVolta, Inc.Inventor: Nicholas K. Eib
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Patent number: 7738078Abstract: The present invention provides an optimized direct write lithography system using optical mirrors. That is, a maskless lithography system is provided. The maskless direct-write lithography system provided uses an array of mirrors configured to operate in a tilting mode, a piston-displacement mode, or both in combination. The controlled mirror array is used as a substitute for the traditional chrome on glass masks. In order to avoid constraining the system to forming edges of patterns aligned with the array of mirrors, gray-scale techniques are used for subpixel feature placement. The direct-writing of a pattern portion may rely on a single mirror mode or a combination of modes.Type: GrantFiled: June 27, 2007Date of Patent: June 15, 2010Assignee: LSI CorporationInventors: Nicholas K. Eib, Ebo Croffie, Neal Callan
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Patent number: 7499146Abstract: The tilt and position of individually controllable element are simultaneously adjusted to allow a greater range of contrasts to be achieved. This can also be used to compensate for cupping of individually controllable elements. Simultaneous adjustment of both the position and tilt of the individually controllable elements can be achieved by two electrodes operable over a range of values.Type: GrantFiled: October 19, 2005Date of Patent: March 3, 2009Assignees: ASML Netherlands B.V., ASML Holding N.V., LSI Logic CorporationInventors: Kars Zeger Troost, Johannes Jacobus Matheus Baselmans, Arno Jan Bleeker, Louis Markoya, Neal Callan, Nicholas K. Eib
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Patent number: 7372547Abstract: The present invention provides methods and apparatus for accomplishing a phase shift lithography process using a off axis light to reduce the effect of zero order light to improve the process window for maskless phase shift lithography systems and methodologies. A lithography system is provided. The lithography system provided uses off axis light beams projected onto a mirror array configured to generate a phase shift optical image pattern. This pattern is projected onto a photoimageable layer formed on the target substrate to facilitate pattern transfer.Type: GrantFiled: December 14, 2004Date of Patent: May 13, 2008Assignee: LSI CorporationInventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
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Patent number: 7270942Abstract: The present invention provides an optimized direct write lithography system using optical mirrors. That is, a maskless lithography system is provided. The maskless direct-write lithography system provided uses an array of mirrors configured to operate in a tilting mode, a piston-displacement mode, or both in combination. The controlled mirror array is used as a substitute for the traditional chrome on glass masks. In order to avoid constraining the system to forming edges of patterns aligned with the array of mirrors, gray-scale techniques are used for subpixel feature placement. The direct-writing of a pattern portion may rely on a single mirror mode or a combination of modes.Type: GrantFiled: April 14, 2004Date of Patent: September 18, 2007Assignee: LSI CorporationInventors: Nicholas K. Eib, Ebo Croffie, Neal Callan
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Patent number: 7264906Abstract: A method and system of optimizing the illumination of a mask in a photolithography process. A specific, preferred method includes the steps of: loading minimum design rules of a layout, loading exposure latitude constraints, loading mask error constraints, loading initial illumination conditions, simulating current illumination conditions, obtaining dose-to-print threshold from the minimum design rules (i.e., lines-and-space feature), applying OPC on the layout using the dose-to-print threshold, calculating DOF using the exposure latitude and mask error constraints, changing the illumination conditions in order to attempt to maximize common DOF with the exposure latitude and mask error constraints, and continuing the process until maximum common DOF is obtained.Type: GrantFiled: March 5, 2004Date of Patent: September 4, 2007Assignee: LSI CorporationInventors: Ebo H. Croffie, Nicholas K. Eib, Mario Garza, Paul Filseth, Lav D. Ivanovic
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Patent number: 7189498Abstract: The present invention provides methods and apparatus for accomplishing a strong phase shift direct write lithography process using reconfigurable optical mirrors. A maskless lithography system is provided. The maskless direct-write lithography system provided uses an array of mirrors configured to operate in a tilting mode, a piston-displacement mode, or both in combination. The controlled mirror array is used to generate strong phase shift optical patterns which are directed onto a photoimageable layer of a substrate in order to facilitate pattern transfer. In order to avoid constraining the system to forming edges of patterns aligned with the array of mirrors, gray-scale techniques are used for subpixel feature placement.Type: GrantFiled: November 19, 2004Date of Patent: March 13, 2007Assignee: LSI Logic CorporationInventors: Nicholas K. Eib, Ebo H. Croffie, Neal P. Callan
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Publication number: 20040241554Abstract: The mask includes a substrate formed of a material having a first index of refraction and a first level of transmittance to a wavelength of light with which the phase shift mask is designed for use. Second portions of the substrate are impregnated with a dopant species, leaving first portions of the substrate unaffected by the dopant species. The second portions of the substrate have a second index of refraction and a second level of transmittance to the wavelength of light. The first index of refraction is not equal to the second index of refraction. The second portions of the substrate shift a phase of the light relative to the first portions of the substrate and thereby increase an effective imaging resolution of the phase shift mask. In this manner, instead of using an etch process or a deposition process to form phase shifting regions of the mask, a doping processing is used instead. Most preferably, an ion implantation process is used.Type: ApplicationFiled: May 29, 2003Publication date: December 2, 2004Applicant: LSI Logic Corporation, Milpitas, CAInventors: Paul Rissman, Nicholas K. Eib, Charles E. May
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Patent number: 6809824Abstract: A process for measuring alignment of latent images in a photoresist layer of an integrated circuit structure on a semiconductor substrate with a test pattern formed in a lower layer on the substrate comprises the steps of forming a test pattern in selected fields of a first layer on a semiconductor substrate, forming a layer of photoresist over the first layer, forming latent images in portions of the photoresist layer lying in the selected fields overlying the test pattern of the first layer; and measuring the alignment of the test pattern in the selected fields of the first layer with the overlying latent images in the photoresist layer using scatterometry.Type: GrantFiled: November 30, 2001Date of Patent: October 26, 2004Assignee: LSI Logic CorporationInventors: Colin D. Yates, Nicholas F. Pasch, Nicholas K. Eib
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Patent number: 6532585Abstract: The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.Type: GrantFiled: November 14, 2000Date of Patent: March 11, 2003Assignee: LSI Logic CorporationInventors: Dusan Petranovic, Ranko Scepanovic, Edwin Jones, Richard Schinella, Nicholas F. Pasch, Mario Garza, Keith K. Chao, John V. Jensen, Nicholas K. Eib
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Patent number: 6499003Abstract: The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.Type: GrantFiled: March 3, 1998Date of Patent: December 24, 2002Assignee: LSI Logic CorporationInventors: Edwin Jones, Dusan Petranovic, Ranko Scepanovic, Richard Schinella, Nicholas F. Pasch, Mario Garza, Keith K. Chao, John V. Jensen, Nicholas K. Eib
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Patent number: 6425117Abstract: The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. A one-dimensional optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g., lines, that are not fully integrated within one cell.Type: GrantFiled: September 29, 1997Date of Patent: July 23, 2002Assignee: LSI Logic CorporationInventors: Nicholas F. Pasch, Nicholas K. Eib, Colin D. Yates, Shumay Dou
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Publication number: 20020004714Abstract: The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.Type: ApplicationFiled: March 3, 1998Publication date: January 10, 2002Inventors: EDWIN JONES, DUSAN PETRANOVIC, RANKO SCEPANOVIC, RICHARD SCHINELLA, NICHOLAS F. PASCH, MARIO GARZA, KEITH K. CHAO, JOHN V. JENSEN, NICHOLAS K. EIB
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Patent number: 6282696Abstract: A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.Type: GrantFiled: March 9, 1999Date of Patent: August 28, 2001Assignee: LSI Logic CorporationInventors: Mario Garza, Nicholas K. Eib, John V. Jensen, Keith K. Chao
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Patent number: 6269472Abstract: Disclosed is a method for correcting a layout design using a design rule checker. The method includes providing a layout design file having the layout design that is to be corrected for optical proximity by the design rule checker. Providing a run set to the design rule checker. The run set includes a plurality of correction values that are used to correct a plurality of features of the layout design that have a selected space dimension. Identifying each of the plurality of features that have the selected space dimension. The method further includes correcting each of the plurality of features that have the selected space dimension with one correction value of the plurality of correction values of the run set. Preferably, the run set is generated from a correction table that has the plurality of correction values.Type: GrantFiled: December 12, 1997Date of Patent: July 31, 2001Assignee: LSI Logic CorporationInventors: Mario Garza, John V. Jensen, Nicholas K. Eib, Keith K. Chao