Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.

Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.

Abstract: A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.

Abstract: A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.

Abstract: Wireless mobile communication device includes unified memory portion; processing units coupled with, and communicating through, unified memory; fault inhibitor coupled with unified memory inhibiting operational fault from nocent informon. Memory, fault inhibitor, and processing units fabricated on monolithic integrated circuit as system-on-chip disposed in wireless mobile personal host. Multiprocessor module includes fault inhibitor and applications and communications processing units and buses, coupled with unified memory. Integrated functional constituent can include coprocessor, accelerator, operational control unit, interprocessor controller, memory controller, bus management unit, bridge, arbiters, and transceiver. Method inhibits operational fault from nocent informon, setting device in operational or fallback state.

Abstract: A microprocessor system having an interrupt controller is provided for use in a mobile communications device. Peripheral processing units generate interrupt requests for sending to the microprocessor. The microprocessor has components for responding to interrupt requests by interrupting current processing and performing an interrupt service routine associated with the interrupt request. The interrupt controller receives interrupt requests directed to the microprocessor from the peripheral processing units and for prioritizes the interrupt requests on behalf of the microprocessor. By providing an interrupt controller for prioritizing interrupt requests on behalf of the microprocessor, the microprocessor therefore need not devote significant internal resources to prioritizing the interrupt request signals.

Abstract: The dual microprocessor system includes one microprocessor configured to perform wireless telephony functions and another configured to perform personal digital assistant (PDA) functions and other non-telephony functions. A memory system and a digital signal processor (DSP) are shared by the microprocessors. By providing a shared memory system, data required by both data microprocessors is conveniently available to both of the microprocessors and their peripheral components thereby eliminating the need to provide separate memory subsystems and further eliminating the need to transfer data back and forth between the separate memory subsystems. By providing a shared DSP, separate DSP devices need not be provided, yet both microprocessors can take advantage of the processing power of the DSP. In a specific example described herein, the microprocessors selectively program the DSP to perform, for example, vocoder functions, voice recognition functions, handwriting recognition functions, and the like.

Abstract: A technique for activating an active-mode high frequency clock following a sleep period for use within a mobile station wherein selected components of the mobile station operate using a low power, low frequency sleep-mode clock during the sleep period and the faster high frequency active-mode clock during non-sleep periods. In one embodiment, the technique is implemented by a device having a wake-up estimation unit for estimating a wake up time using the sleep-mode clock and a frequency drift compensation unit for compensating for any error in the estimated wake up time caused by frequency drift in the sleep-mode clock. An off-set time compensation unit is also provided for compensating for a lack of precision in the low frequency sleep-mode clock resulting in a possible error in the estimated wake up time. The lack of precision can result in an initial timing off-set error at the beginning of the sleep period and an final timing off-set error at the end of the sleep period.

Abstract: A microprocessor system having an interrupt controller is provided for use in a mobile communications device. Peripheral processing units generate interrupt requests for sending to the microprocessor. The microprocessor has components for responding to interrupt requests by interrupting current processing and performing an interrupt service routine associated with the interrupt request. The interrupt controller receives interrupt requests directed to the microprocessor from the peripheral processing units and for prioritizes the interrupt requests on behalf of the microprocessor. By providing an interrupt controller for prioritizing interrupt requests on behalf of the microprocessor, the microprocessor therefore need not devote significant internal resources to prioritizing the interrupt request signals.

Abstract: The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory.

Abstract: The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory.

Abstract: A method and circuit for controlling a mobile station operating in a slotted paging environment. The circuit comprises a low power clock for generating a low frequency clock signal; a clock signal generator for generating a high frequency clock signal; a synchronization logic circuit for synchronizing the low frequency clock signal to the high frequency clock signal; a frequency error estimator for measuring an estimated low frequency clock error; and a sleep controller for removing power from the clock signal generator for the corrected sleep duration value, thereby conserving power between assigned paging slots. During the awake time, the low frequency clock signal is resynchronized to the high frequency clock, thereby correcting for any frequency error in the less accurate low power clock during sleep mode.

Abstract: The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory.