Patents by Inventor Nicholas Ka Ming Stevens-Yu

Nicholas Ka Ming Stevens-Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10534047
    Abstract: Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity are disclosed. For example, a TMR sensor may be used as a biosensor to detect the presence of biological materials. In aspects disclosed herein, free layers of at least two TMR devices in a TMR sensor are fabricated to exhibit different magnetic properties from each other (e.g., MR ratio, magnetic anisotropy, coercivity) so that each TMR device will exhibit a different change in resistance to a given magnetic stray field for increased magnetic field detection sensitivity. For example, the TMR devices may be fabricated to exhibit different magnetic properties such that one TMR device exhibits a greater change in resistance in the presence of a smaller magnetic stray field, and another TMR device exhibits a greater change in resistance in the presence of a larger magnetic stray field.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Wei-Chuan Chen, Wah Nam Hsu, Xia Li, Seung Hyuk Kang, Nicholas Ka Ming Stevens-Yu
  • Publication number: 20190342106
    Abstract: Physically unclonable function (PUF) circuits employing multiple PUF memories to decouple a PUF challenge input from a PUF response output for enhanced security. The PUF circuit includes a PUF challenge memory and a PUF response memory. In response to a read operation, the PUF challenge memory uses a received PUF challenge input data word to address PUF challenge memory arrays therein to generate a plurality of intermediate PUF challenge output data words. The PUF response memory is configured to generate a second, final PUF response output data word in response to intermediate PUF challenge output data words. In this manner, it is more difficult to learn the challenge-response behavior of the PUF circuit, because the PUF challenge input data word does not directly address a memory array that stores memory states representing final logic values in the PUF response output data word.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 7, 2019
    Inventors: Xia Li, Seung Hyuk Kang, Nicholas Ka Ming Stevens-Yu
  • Patent number: 10410714
    Abstract: Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations are disclosed. In one aspect, an MLC SRAM cell includes SRAM bit cells, wherein data values stored in SRAM bit cells correspond to a multiple-bit value stored in the MLC SRAM cell that serves as first operand in multiplication operation. Voltage applied to read bit line is applied to each SRAM bit cell, wherein the voltage is an analog representation of a multiple-bit value that serves as a second operand in the multiplication operation. For each SRAM bit cell, if a particular binary data value is stored, a current correlating to the voltage of the read bit line is added to a current sum line. A magnitude of current on the current sum line is an analog representation of a multiple-bit product of the first operand multiplied by the second operand.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Seung Hyuk Kang, Venkat Rangan, Rashid Ahmed Akbar Attar, Nicholas Ka Ming Stevens-Yu
  • Publication number: 20190088309
    Abstract: Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations are disclosed. In one aspect, an MLC SRAM cell includes SRAM bit cells, wherein data values stored in SRAM bit cells correspond to a multiple-bit value stored in the MLC SRAM cell that serves as first operand in multiplication operation. Voltage applied to read bit line is applied to each SRAM bit cell, wherein the voltage is an analog representation of a multiple-bit value that serves as a second operand in the multiplication operation. For each SRAM bit cell, if a particular binary data value is stored, a current correlating to the voltage of the read bit line is added to a current sum line. A magnitude of current on the current sum line is an analog representation of a multiple-bit product of the first operand multiplied by the second operand.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 21, 2019
    Inventors: Xia Li, Seung Hyuk Kang, Venkat Rangan, Rashid Ahmed Akbar Attar, Nicholas Ka Ming Stevens-Yu
  • Publication number: 20180284200
    Abstract: Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity are disclosed. For example, a TMR sensor may be used as a biosensor to detect the presence of biological materials. In aspects disclosed herein, free layers of at least two TMR devices in a TMR sensor are fabricated to exhibit different magnetic properties from each other (e.g., MR ratio, magnetic anisotropy, coercivity) so that each TMR device will exhibit a different change in resistance to a given magnetic stray field for increased magnetic field detection sensitivity. For example, the TMR devices may be fabricated to exhibit different magnetic properties such that one TMR device exhibits a greater change in resistance in the presence of a smaller magnetic stray field, and another TMR device exhibits a greater change in resistance in the presence of a larger magnetic stray field.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Inventors: Wei-Chuan Chen, Wah Nam Hsu, Xia Li, Seung Hyuk Kang, Nicholas Ka Ming Stevens-Yu