Patents by Inventor Nicholas Kucharewski, III

Nicholas Kucharewski, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scalable, low latency, deep buffered switch architecture
    Patent number: 10728156
    Abstract: A switch architecture includes an ingress module, ingress fabric interface module, and a switch fabric. The switch fabric communicates with egress fabric interface modules and egress modules. The architecture implements multiple layers of congestion management. The congestion management may include fast acting link level flow control and more slowly acting end-to-end flow control. The switch architecture simultaneously provides high scalability, with low latency and low frame loss.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: July 28, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Bruce Hui Kwan, Puneet Agarwal, Mohan Kalkunte, Nicholas Kucharewski, III
  • Scalable, Low Latency, Deep Buffered Switch Architecture
    Publication number: 20140241160
    Abstract: A switch architecture includes an ingress module, ingress fabric interface module, and a switch fabric. The switch fabric communicates with egress fabric interface modules and egress modules. The architecture implements multiple layers of congestion management. The congestion management may include fast acting link level flow control and more slowly acting end-to-end flow control. The switch architecture simultaneously provides high scalability, with low latency and low frame loss.
    Type: Application
    Filed: October 3, 2013
    Publication date: August 28, 2014
    Applicant: Broadcom Corporation
    Inventors: Bruce Hui Kwan, Puneet Agarwal, Mohan Kalkunte, Nicholas Kucharewski, III