Abstract: Systems and methods for maintaining performance of an integrated circuit are disclosed. One embodiment of a system may comprise a bus clock signal that is a copy of a system clock signal that controls the timing associated with transferring data over the bus, a data clock signal that is designed to lead the system clock by a portion of a clock cycle to drive data over the bus ahead of the bus clock signal, an output latch device that drives data over the data bus in response to an edge of the data clock signal and a skew corrector that mitigates racing of data over the data bus in the event that the data clock lags the bus clock.

Abstract: An IC layout design process and system involves placing an adjustable capacitor cell having a plurality of sub-cells, each with a polysilicon shape disposed over a corresponding active area shape. The polysilicon shapes are electrically coupled to a first power rail and the active area shapes are electrically coupled to a second power rail. The sub-cells of the adjustable capacitor cell are operable to be modified to satisfy a density measurement associated with the IC's fabrication flow.

Abstract: An IC layout design process and system involves placing an adjustable capacitor cell having a plurality of sub-cells, each with a polysilicon shape disposed over a corresponding active area shape. The polysilicon shapes are electrically coupled to a first power rail and the active area shapes are electrically coupled to a second power rail. The sub-cells of the adjustable capacitor cell are operable to be modified to satisfy a density measurement associated with the IC's fabrication flow.