Patents by Inventor Nicholas Paluzzi

Nicholas Paluzzi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7383492
    Abstract: A system and method for determining data integrity as such data passes through a FIFO. A generator is provided for appending a bit in a predetermined bit location in each packet pushed into the FIFO in response clock signals. The appended bit is a function of the information pushed into the FIFO. A checker is provided for providing an indication of the information integrity in response to bits produced at an output of the FIFO in the predetermined bit location. In one embodiment, the generator is a parity generator and the checker is a parity checker. In one embodiment, during an initial test mode, one parity type is introduced into the FIFO by the parity generator and the opposite parity type is checked at the output of the FIFO by the parity checker to determine whether the parity checker is able to produce parity error signals. In another embodiment, the generator is a packet delimiter generator and the checker is a packet delimiter checker.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: June 3, 2008
    Assignee: EMC Corporation
    Inventors: Philip M. Sailer, Nicholas Paluzzi, Avinash Kallat, Stephen L. Scaringella, Krzysztof Dobecki
  • Patent number: 7099971
    Abstract: A system and method wherein a bus arbiter grants access to a bus to bus-coupled clients in order to provide access to a memory resource shared by the clients in response to “address retry” conditions induced by such clients. The bus arbiter provides access to the bus in response to whether one of the requesting clients experienced an “address retry” condition during its previous bus access. If such an address retry condition was experienced during its previous bus access, the bus arbiter grants such one of the requesting clients access to the bus at the earliest opportunity. Otherwise, the bus arbiter provides bus access to the requesting one, or ones, of the clients based on criteria independent of “address retry” conditions being induced on the bus.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: August 29, 2006
    Assignee: EMC Corporation
    Inventors: Nicholas Paluzzi, Philip M. Sailer, Stephen L. Scaringella
  • Patent number: 6901468
    Abstract: A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: May 31, 2005
    Assignee: EMC Corporation
    Inventor: Nicholas Paluzzi
  • Publication number: 20040187053
    Abstract: A system and method for determining data integrity as such data passes through a FIFO. A generator is provided for appending a bit in a predetermined bit location in each packet pushed into the FIFO in response clock signals. The appended bit is a function of the information pushed into the FIFO. A checker is provided for providing an indication of the information integrity in response to bits produced at an output of the FIFO in the predetermined bit location. In one embodiment, the generator is a parity generator and the checker is a parity checker. In one embodiment, during an initial test mode, one parity type is introduced into the FIFO by the parity generator and the opposite parity type is checked at the output of the FIFO by the parity checker to determine whether the parity checker is able to produce parity error signals. In another embodiment, the generator is a packet delimiter generator and the checker is a packet delimiter checker.
    Type: Application
    Filed: March 20, 2003
    Publication date: September 23, 2004
    Inventors: Philip M. Sailer, Nicholas Paluzzi, Avinash Kallat, Stephen L. Scaringella, Krzysztof Dobecki
  • Patent number: 6684268
    Abstract: A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: January 27, 2004
    Assignee: EMC Corporation
    Inventor: Nicholas Paluzzi
  • Patent number: 6631433
    Abstract: A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: October 7, 2003
    Assignee: EMC Corporation
    Inventor: Nicholas Paluzzi