Abstract: Various embodiments of the present technology provide a method and apparatus for an image sensor. In various embodiments, the apparatus provides a driver circuit connected to a plurality of electrically distinct pixel groups to provide the pixel groups with a control signal. A delay measurement circuit is connected to the driver circuit and at least one of the pixel groups to measure a time delay of the control signal. A row control circuit is connected to the delay measurement circuit to receive the measured time delay and, in turn, deliver, via the driver circuit, the control signal to all pixel groups in a single row substantially simultaneously.

Abstract: An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of tiles in a reticle set. Multiple instantiations of a same circuitry block on a given tile may be patterned and formed on the image sensor die. The image sensor die may include circuitry configured to enable testing of one or more instantiations of the same circuitry block. The image sensor die may include memory circuitry for storing indications of a functional instantiation of the multiple instances and may use the functional instantiation for normal operation.

Abstract: Various embodiments of the present technology provide a method and apparatus for an image sensor. In various embodiments, the apparatus provides a driver circuit connected to a plurality of electrically distinct pixel groups to provide the pixel groups with a control signal. A delay measurement circuit is connected to the driver circuit and at least one of the pixel groups to measure a time delay of the control signal. A row control circuit is connected to the delay measurement circuit to receive the measured time delay and, in turn, deliver, via the driver circuit, the control signal to all pixel groups in a single row substantially simultaneously.

Abstract: An image sensor may include a pixel array having pixels arranged in rows and columns, column readout circuitry, and control circuitry. Column readout circuitry may include corresponding readout circuits each coupled to a corresponding column path for a respective column of pixels. The readout circuits may each include signal processing circuits such as correlated double sampling circuitry and analog-to-digital converter circuitry. To reduce peak-to-average power ratio, during the signal processing operations for each pixel row, the control circuitry may control the signal processing circuits to perform time-domain multiplexing across the pixel columns to activate the signal processing circuits at varied times within the row time. If desired, the pattern of time-domain multiplexing may be varied across the signal processing operations for different pixel rows and/or for different image frames.

Abstract: Various embodiments of the present technology provide a method and apparatus for an image sensor. In various embodiments, the apparatus provides a driver circuit connected to a plurality of electrically distinct pixel groups to provide the pixel groups with a control signal. A delay measurement circuit is connected to the driver circuit and at least one of the pixel groups to measure a time delay of the control signal. A row control circuit is connected to the delay measurement circuit to receive the measured time delay and, in turn, deliver, via the driver circuit, the control signal to all pixel groups in a single row substantially simultaneously.

Abstract: An image sensor may include a pixel array, row control circuitry, and column readout circuitry. The row control circuitry may operate the pixel array in a global shutter mode of operation. In particular, timing control circuitry may provide global timing clock signals associated with a global photodiode reset event and a global photodiode charge transfer event to row driver circuitry providing control signals to each row in the array. Each driver circuitry may include a time delay circuit that delays the global timing clock signal by different amounts across the rows. Therefore, these global events may be offset on a per-row or per-row group basis, thereby mitigating power surges associated with global events. Further, by offsetting the global photodiode reset and charge transfer events using the same delay for a given row, the same global integration time may be preserved across different rows.

Abstract: An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of tiles in a reticle set. Multiple instantiations of a same circuitry block on a given tile may be patterned and formed on the image sensor die. The image sensor die may include circuitry configured to enable testing of one or more instantiations of the same circuitry block. The image sensor die may include memory circuitry for storing indications of a functional instantiation of the multiple instances and may use the functional instantiation for normal operation.

Abstract: An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of tiles in a reticle set. Multiple instantiations of a same circuitry block on a given tile may be patterned and formed on the image sensor die. The image sensor die may include circuitry configured to enable testing of one or more instantiations of the same circuitry block. The image sensor die may include memory circuitry for storing indications of a functional instantiation of the multiple instances and may use the functional instantiation for normal operation.

Abstract: An image sensor may include a pixel array coupled to column readout circuitry. The pixel array may be split into multiple sub-arrays. Readout circuitry may be shared between multiple columns in each sub-array or in the pixel array. The readout circuitry may be coupled to at least first and second pixels in first and second different columns. The readout circuitry may include amplifier circuitry that receives signals from both the first and second pixels. Two input capacitors for the amplifier circuitry may form two corresponding memory circuits, for the first and second columns, respectively. Two feedback capacitors for the amplifier circuitry may form two corresponding memory circuits, for the first and second columns, respectively. The readout circuitry may be configured to perform a shared reset level readout operation for the first and second pixels and to perform separate correlated double sampling readout operations for the first and second pixels.

Abstract: An imaging device may have an array of image sensor pixels arranged in rows and columns and column readout circuitry coupled to the array. The rows of pixels may receive drive signals from row driver circuitry, and the drive signals may be sent from timing circuitry based on the locations of rows within the array. In particular, rows closer to the readout circuitry may require less settling time and therefore be driven faster than the rows further from the readout circuitry. All of the rows may be driven in a single direction, or the array of pixels may have a cut, in which case rows above the cut may be driven up and rows below the cut may be driven down. A frame buffer may be used to store the signals generated by the rows of pixels and may account for the asynchronous read out of image data.

Abstract: An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of physical tiles in a reticle set. The physical tiles may include a center tile forming pixel circuitry on the image sensor die and peripheral tiles forming non-pixel circuitry on the image sensor die. Each of the physical tiles may be sized based on an integer multiple of a virtual unit tile. As such, the physical tiles may have dimensions that are not required to be an integer multiple of the smallest physical tile. The step and repeat exposure process may use the unit lengths of the virtual unit tile to properly position the die relative to the processing tools.

Abstract: An image sensor may include an array of image pixels that is coupled to column readout circuitry, which may read out charge generated by the image pixels. The column readout circuitry may include a column amplifier having analog memory cells. The analog memory cells may include a high gain capacitor and a low gain capacitor coupled in parallel between a column of the image pixels and an input of the column amplifier. A feedback capacitor may be coupled between the input and an output of the column amplifier. High and low gain select switches respectively coupled to the high and low gain capacitors may allow for the output of high and low gain reset values and image signals, which may be used in correlated double sampling operations and which may increase the dynamic range of the image sensor.

Abstract: A radio frequency tuner comprises one or more tracking filters ahead of at least one frequency changer. A controller has a filter alignment mode and a reception mode. Each filter has one or more resonant networks comprising an inductance and a switched capacitor network which is digitally controlled for selecting the network resonant frequency. In the alignment mode, the controller determines the difference between the nominal and actual capacitances of the network for achieving a known resonant frequency in order to determine a correction factor for the capacitor network. The correction factor is then used during normal reception by the tuner.

Abstract: A radio frequency tuner is provided having inputs for receiving signals in common or overlapping frequency ranges from distribution networks. Each input is connected to a respective first converter, for example performing upconversion to a first intermediate frequency above the RF frequency ranges of the incoming signals. The first frequency changers are arranged to be active one at a time. The outputs of the first frequency changers are supplied to a second frequency changer which performs downconversion on the output signal of the active first converter to convert a selected channel from one of the distribution networks to a second intermediate frequency. Sufficient RF isolation may therefore be provided without requiring mechanical switching components such as RF relays.

Abstract: A quadrature frequency changer comprising first and second mixers and a local oscillator and a tuner and modulator including the quadrature frequency changer are provided. The local oscillator provides first and second commutating signals which are nominally in phase-quadrature and includes an arrangement for changing the phase of the first commutating signal by 180° to provide a third commutating signal. The first mixer comprises first and second mixing stages for mixing an input signal with the first and second commutating signals and a summer for summing the mixer stage output signals. The second mixer comprises third and fourth mixing stages for mixing the same or a different input signal with the second and third commuting signals and a summer for summing the third and fourth mixer stage output signals.

Abstract: A variable signal delaying circuit comprising an analog delay line having a control input for controlling the variable delay. A phase detector compares the input and output signals of the delaying circuit and supplies an output signal to a charge pump and integrator. A pulse stream generating arrangement produces pulse streams of different pulse widths and pulse control logic controls a selector for selecting any one of the pulse streams. In a first mode of operation, the control logic monitors the charge pump/filter output and selects the pulse stream which minimizes change in the output. The selection is fixed and the output of the charge pump/filter is then supplied as a correction signal to the control input of the analog delay line. Such an arrangement may be used to maintain minimum phase imbalance in I and Q signal paths of a quadrature frequency converter.

Abstract: A method is provided for reducing imbalance in a quadrature frequency converter. A test tone generator controlled by an alignment controller supplies a test signal to the input of the frequency converter. A starting point is selected in a solution space addressed by I and Q corrections. The starting point comprises in-phase (I) and quadrature (Q) phase correction values. A test is then performed to determine the best direction of movement in the I/Q phase correction plane in order to reduce phase imbalance. The I and Q phase correction values are then moved in that direction towards a phase imbalance minimum.

Abstract: A radio frequency tuner includes a first quadrature frequency changer, I and Q filters which are electronically adjustable, and a second quadrature frequency changer. During alignment of the filters, an alignment controller connects a test tone generator to the input of the frequency converter and the generator supplies a sequence of test tones of different accurately known frequencies. The amplitude of the resulting signals at the output of one of the filters is measured by a level detector. The controller compares the measured levels with a desired frequency response and adjusts the filter accordingly. The controller then causes the generator to supply a sequence of two test tones of different frequencies and a differential phase detector measures the phase difference between the output signals of the mixers of the second frequency changer.

Abstract: A front end for a radio frequency tuner, for example for connection to a cable distribution network, including an input connected to a signal path comprising an LNA connected via an AGC stage to a signal splitter. The input path has a bandwidth sufficiently wide to pass all of the channels in an input signal and has a substantially constant voltage standing wave ratio over the bandwidth. The splitter supplies identical signals to several filtering paths, each of which comprises a fixed filter. The paths are selectable one at a time and the filters divide the input frequency band into a plurality of contiguous or slightly overlapping sub-bands. The output of the front end is supplied to, for example, a double conversion arrangement comprising an upconverter and a downconverter with first and second IF filters.

Abstract: A tuner arrangement is provided comprising one or more tuners. Each tuner has two or more frequency changers, each comprising a mixer and a local oscillator. A controller controls the local oscillators in response to receipt of a channel select request. The controller determines the nominal frequencies of the local oscillators for tuning the selected channel and then performs a calculation to determine whether any beat frequencies between harmonics greater than the first harmonic of the local oscillators lie within the frequency band at the tuner output occupied by the selected channel. If so, the controller shifts the local oscillator frequencies so as to move the potentially interfering products outside the utilised band and then tunes the local oscillators appropriately.