Patents by Inventor Nicholas Pavey

Nicholas Pavey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • State coverage tool
    Patent number: 7133817
    Abstract: A method of verifying a digital hardware design simulated in a hardware design language (HDL). States to be verified are defined, including signal values for each component within the hardware design. A test is applied to the hardware design, such that traces of internal signals within the hardware design are recorded. Each trace includes signal data, time data and at least the internal signals associated with the components. The traces are processed to ascertain whether the plurality of components simultaneously had the signal values associated with the state, thereby to ascertain whether the state was achieved.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: November 7, 2006
    Assignee: STMicroelectronics Limited
    Inventor: Nicholas Pavey
  • Method of testing integrated circuitry at system and module level
    Patent number: 6694497
    Abstract: A method of testing integrated circuitry at a module and system level, in which an intermediate test, including multiple testing steps, is generated in a third programming language. The intermediate test is converted into an abstract representation of the testing steps. System and module level tests based on the abstract representation are generated in second and first respective programming languages. The integrated circuitry is then tested at system level with the system-level test and at module level with the module level test.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: February 17, 2004
    Assignee: STMicroelectronics Limited
    Inventor: Nicholas Pavey
  • State coverage tool
    Publication number: 20030167160
    Abstract: A method of verifying a digital hardware design simulated in a hardware design language (HDL). States to be verified are defined, including signal values for each component within the hardware design. A test is applied to the hardware design, such that traces of internal signals within the hardware design are recorded. Each trace includes signal data, time data and at least the internal signals associated with the components. The traces are processed to ascertain whether the plurality of components simultaneously had the signal values associated with the state, thereby to ascertain whether the state was achieved.
    Type: Application
    Filed: February 12, 2002
    Publication date: September 4, 2003
    Inventor: Nicholas Pavey
  • Method of testing integrated circuitry at system and module level
    Publication number: 20030110456
    Abstract: A method of testing integrated circuitry at a module and system level, in which an intermediate test, including multiple testing steps, is generated in a third programming language. The intermediate test is converted into an abstract representation of the testing steps. System and module level tests based on the abstract representation are generated in second and first respective programming languages. The integrated circuitry is then tested at system level with the system-level test and at module level with the module level test.
    Type: Application
    Filed: October 26, 2001
    Publication date: June 12, 2003
    Inventor: Nicholas Pavey