Abstract: A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.

Abstract: A computer processor includes a dispatch stage and a dependency skipping execution unit. The dispatch stage is configured to dispatch a plurality of instructions that include a general purpose instruction configured to produce first data, a dependent instruction configured to produce second data, and an indirect dependent instruction configured to produce third data. The dependency skipping execution unit is configured to monitor the plurality of instructions and to process the indirect dependent instruction in response to the general purpose instruction producing the first data. The indirect dependent instruction is issued independently from the second data produced by the indirect dependent instruction.

Abstract: A computer processor includes an instruction pipeline configured to dispatch a plurality of branch-to-count (BCNT) instructions and an instruction fetch unit (IFU). The IFU is configured to execute an instruction loop for fetching a targeted number of BCNT instructions from the instruction pipeline and to monitor a loop counter that counts a number of fetched BCNT instructions that are actually fetched from the instruction pipeline in response to executing the instruction loop. The IFU resolves a final BCNT instruction included in the instruction loop in response to the number of fetched BCNT instructions reaching a target loop count value.

Abstract: A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.

Abstract: A computer processor includes a dispatch stage and a dependency skipping execution unit. The dispatch stage is configured to dispatch a plurality of instructions that include a general purpose instruction configured to produce first data, a dependent instruction configured to produce second data, and an indirect dependent instruction configured to produce third data. The dependency skipping execution unit is configured to monitor the plurality of instructions and to process the indirect dependent instruction in response to the general purpose instruction producing the first data. The indirect dependent instruction is issued independently from the second data produced by the indirect dependent instruction.

Abstract: Aspects are provided for sharing instruction cache footprint between multiple threads using instruction cache set/way pointers and a tracking table. The tracking table is built up over time for shared pages, even when the instruction cache has no access to real addresses or translation information. A set/way pointer to an instruction cache line is derived from the system memory address associated with a first thread's instruction fetch. The set/way pointer is stored as a surrogate for the system memory address in both an instruction cache directory (IDIR) and a tracking table. Another set/way pointer to an instruction cache line is derived from the system memory address associated with a second thread's instruction fetch. A match is detected between the set/way pointer and the other set/way pointer. The instruction cache directory is updated to indicate that the instruction cache line is shared between multiple threads.

Abstract: Aspects are provided for sharing instruction cache footprint between multiple threads. A set/way pointer to an instruction cache line is derived from a system memory address associated with an instruction fetch from a memory page. It is determined that the instruction cache line is shareable between a first thread and a second thread. An alias table entry is created indicating that other instruction cache lines associated with the memory page are also shareable between threads. Another instruction fetch is received from another thread requesting an instruction from another system memory address associated with the memory page. A further set/way pointer to another instruction cache line is derived from the other system memory address. It is determined that the other instruction cache line is shareable based on the alias table entry.

Abstract: Aspects are provided for sharing instruction cache footprint between multiple threads. A set/way pointer to an instruction cache line is derived from a system memory address associated with an instruction fetch from a memory page. It is determined that the instruction cache line is shareable between the first thread and the second thread. An alias table entry is created indicating that other instruction cache lines associated with the memory page are also shareable between threads. Another instruction fetch is received from another thread requesting an instruction from another system memory address associated with the memory page. A further set/way pointer to another instruction cache line is derived from the other system memory address. It is determined that the other instruction cache line is sharable based on the alias table entry.

Abstract: Aspects are provided for sharing instruction cache footprint between multiple threads using instruction cache set/way pointers and a tracking table. The tracking table is built up over time for shared pages, even when the instruction cache has no access to real addresses or translation information. A set/way pointer to an instruction cache line is derived from the system memory address associated with a first thread's instruction fetch. The set/way pointer is stored as a surrogate for the system memory address in both an instruction cache directory (IDIR) and a tracking table. Another set/way pointer to an instruction cache line is derived from the system memory address associated with a second thread's instruction fetch. A match is detected between the set/way pointer and the other set/way pointer. The instruction cache directory is updated to indicate that the instruction cache line is shared between multiple threads.

Abstract: Branch prediction in an instruction using a tag orientation predictor (TOP) is described. When a branch instruction is hotly mis-predicted by a hybrid branch predictor, the branch is tracked over a longer time period using the TOP. Once the TOP has collected enough data to confidently predict a branch prediction, the TOP is used to override a branch prediction from the hybrid predictor when the TOP branch prediction.

Abstract: Load store addressing can include a processor, which fuses two consecutive instruction determined to be prefix instructions and treats the two instructions as a single fused instruction. The prefix instruction of the fused instruction is auto-finished at dispatch time in an issue unit of the processor. A suffix instruction of the fused instruction and its fields and the prefix instruction's fields are issued from an issue queue of the issue unit, wherein an opcode of the suffix instruction is issued to a load store unit of the processor, and fields of the fused instruction are issued to the execution unit of the processor. The execution unit forms operands of the suffix instruction, at least one operand formed based on a current instruction address of the single fused instruction. The load store unit executes the suffix instruction using the operands formed by the execution unit.

Abstract: Load store addressing can include a processor, which fuses two consecutive instruction determined to be prefix instructions and treats the two instructions as a single fused instruction. The prefix instruction of the fused instruction is auto-finished at dispatch time in an issue unit of the processor. A suffix instruction of the fused instruction and its fields and the prefix instruction's fields are issued from an issue queue of the issue unit, wherein an opcode of the suffix instruction is issued to a load store unit of the processor, and fields of the fused instruction are issued to the execution unit of the processor. The execution unit forms operands of the suffix instruction, at least one operand formed based on a current instruction address of the single fused instruction. The load store unit executes the suffix instruction using the operands formed by the execution unit.

Abstract: A computer processor includes an issue queue to receive an instruction, and one or more execution units to generate a condition code bit corresponding to the instruction. A branch condition queue is in signal communication with the issue queue, and receives the instruction from the issue queue before the at least one execution unit generates the condition code bit.

Abstract: Branch prediction in an instruction using a tag orientation predictor (TOP) is described. When a branch instruction is hotly mis-predicted by a hybrid branch predictor, the branch is tracked over a longer time period using the TOP. Once the TOP has collected enough data to confidently predict a branch prediction, the TOP is used to override a branch prediction from the hybrid predictor when the TOP branch prediction.

Abstract: A processor-implemented method is provided. The processor-implemented includes reading, by a processor, an instruction stream by fetching instructions from an instruction cache of the processor. The processor then executes a branch prediction operation based on a context of the instruction stream and an index when one of the instructions includes a branch instruction. The branch prediction operation output a prediction and a context. The processor then compares the context of the instruction stream and the context from the branch prediction operation to determine whether to execute a stop fetch.

Abstract: Operation of a multi-slice processor implementing a tagged geometric history length prediction unit and an effective address table aligned with an update table, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving, at an effective address table and at a TAGE update table, information for a branch instruction dispatched to an execution slice, wherein the effective address table and the TAGE update table are in alignment; responsive to the branch instruction being taken, updating the effective address table and the TAGE update table to indicate the branch instruction being taken; and updating, in dependence upon the alignment between the effective address table and the TAGE update table, the TAGE branch prediction unit with update information from both the effective address table and the TAGE update table.

Abstract: A processor-implemented method is provided. The processor-implemented includes reading, by a processor, an instruction stream by fetching instructions from an instruction cache of the processor. The processor then executes a branch prediction operation based on a context of the instruction stream and an index when one of the instructions includes a branch instruction. The branch prediction operation output a prediction and a context. The processor then compares the context of the instruction stream and the context from the branch prediction operation to determine whether to execute a stop fetch.

Abstract: A computer processor includes a branch prediction unit that includes a local branch predictor and a global branch predictor. Managing power consumption in such a computer processor includes, for each of a plurality of branch instructions: performing, by the local branch predictor, a local branch prediction; performing, by each of the global branch predictors, a global branch prediction; determining to utilize the local branch prediction over the global branch predictions as a branch prediction for the branch instruction; incrementing a value of a counter; determining whether the value of the counter exceeds a predetermined threshold; and if the value of the counter exceeds the predetermined threshold, powering down at least one of the global branch predictors and configuring the branch prediction unit to bypass the powered down global branch predictor for branch predictions of subsequent branch instructions.

Abstract: Executing system call vectored (SCV) instructions in a multi-slice processor including receiving, by an instruction fetch unit, a SCV instruction, wherein the SCV instruction is a system call from an operating system; sending the SCV instruction to a branch issue queue; determining, by the branch issue queue, that the SCV instruction is next-to-complete; issuing the SCV instruction to a branch resolution unit; and executing the SCV instruction by the branch resolution unit.

Abstract: A computer processor includes an issue queue to receive an instruction, and one or more execution units to generate a condition code bit corresponding to the instruction. A branch condition queue is in signal communication with the issue queue, and receives the instruction from the issue queue before the at least one execution unit generates the condition code bit.