Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

Abstract: Systems, apparatuses, and methods related to epitaxial growth on semiconductor structures are described. An apparatus may include a working surface of a substrate material and a storage node connected to an active area of an access device on the working surface. The apparatus may also include a material epitaxially grown over the storage node contact to enclose a non-solid space between the storage node contact and passing sense lines.

Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Abstract: Systems, apparatuses, and methods related to epitaxial growth on semiconductor structures are described. An apparatus may include a working surface of a substrate material and a storage node connected to an active area of an access device on the working surface. The apparatus may also include a material epitaxially grown over the storage node contact to enclose a non-solid space between the storage node contact and passing sense lines.

Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.