Patents by Inventor Nicholas S. HAEHN
Nicholas S. HAEHN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136326Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.Type: ApplicationFiled: December 28, 2023Publication date: April 25, 2024Inventors: Wei LI, Edvin CETEGEN, Nicholas S. HAEHN, Ram S. VISWANATH, Nicholas NEAL, Mitul MODI
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Patent number: 11942393Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.Type: GrantFiled: February 4, 2020Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Wei Li, Edvin Cetegen, Nicholas S. Haehn, Mitul Modi, Nicholas Neal
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Patent number: 11901333Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.Type: GrantFiled: October 8, 2019Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Wei Li, Edvin Cetegen, Nicholas S. Haehn, Ram S. Viswanath, Nicholas Neal, Mitul Modi
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Patent number: 11832419Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.Type: GrantFiled: December 20, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Nicholas Neal, Nicholas S. Haehn, Je-Young Chang, Kyle Arrington, Aaron McCann, Edvin Cetegen, Ravindranath V. Mahajan, Robert L. Sankman, Ken P. Hackenberg, Sergio A. Chan Arguedas
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Publication number: 20230343723Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Inventors: Nicholas NEAL, Nicholas S. HAEHN, Sergio CHAN ARGUEDAS, Edvin CETEGEN, Jacob VEHONSKY, Steve S. CHO, Rahul JAIN, Antariksh Rao Pratap SINGH, Tarek A. IBRAHIM, Thomas HEATON
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Patent number: 11776864Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.Type: GrantFiled: July 15, 2019Date of Patent: October 3, 2023Assignee: Intel CorporationInventors: Jacob Vehonsky, Nicholas S. Haehn, Thomas Heaton, Steve S. Cho, Rahul Jain, Tarek Ibrahim, Antariksh Rao Pratap Singh, Edvin Cetegen, Nicholas Neal, Sergio Chan Arguedas
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Publication number: 20230238355Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.Type: ApplicationFiled: March 28, 2023Publication date: July 27, 2023Inventors: Wei LI, Edvin CETEGEN, Nicholas S. HAEHN, Ram S. VISWANATH, Nicholas NEAL, Mitul MODI
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Publication number: 20230087810Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Jeremy D. ECTON, Kristof DARMAWIKARTA, Suddhasattwa NAD, Oscar OJEDA, Bai NIE, Brandon C. MARIN, Gang DUAN, Jacob VEHONSKY, Onur OZKAN, Nicholas S. HAEHN
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Publication number: 20230086180Abstract: A semiconductor device may include a first plate-like element having a first substantially planar connection surface with a first connection pad and a second plate-like element having a second substantially planar connection surface with a second connection pad corresponding to the first connection pad. The device may also include a connection electrically and physically coupling the first and second plate-like elements and arranged between the first and second connection pads. The connection may include a deformed elongate element arranged on the first connection pad and extending toward the second connection pad and solder in contact with the second connection pad and the elongate element.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: Onur Ozkan, Edvin Cetegen, Steve Cho, Nicholas S. Haehn, Jacob Vehonsky, Gang Duan
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Publication number: 20230086649Abstract: An apparatus is described. The apparatus includes I/O structures having pads and solder balls to couple with a semiconductor chip, wherein, a first subset of pads and/or solder balls of the pads and solder balls that approach the semiconductor chip during coupling of the semiconductor chip to the I/O structures are thinner than a second subset of pads and/or solder balls of the pads and solder balls that move away from the semiconductor chip during the coupling of the semiconductor chip to the I/O structures.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Onur OZKAN, Edvin CETEGEN, Steve CHO, Nicholas S. HAEHN, Jacob VEHONSKY
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Publication number: 20220384306Abstract: A thermal interface structure for facilitating heat transfer from an integrated circuit device to a heat dissipation device may be fabricated to include at least one conductive wire structure wherein each conductive wire structure includes a conductive wire having a first end, a first barrier layer adjacent the first end of the conductive wire, and a first solder structure adjacent the first barrier layer. The thermal interface structure may further include an encapsulation material substantially encapsulating each conductive wire structure and a first solder layer abutting the encapsulation material and abutting the first solder structure of each conductive wire structure.Type: ApplicationFiled: May 26, 2021Publication date: December 1, 2022Applicant: Intel CorporationInventors: Weihua Tang, Chandra Mohan Jha, Nicholas S. Haehn
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Patent number: 11502008Abstract: An integrated circuit assembly including a substrate having a surface including at least one area including contact points operable for connection with an integrated circuit die; and at least one ring surrounding the at least one area, the at least one ring including an electrically conductive material. A method of forming an integrated circuit assembly including forming a plurality of electrically conductive rings around a periphery of a die area of a substrate selected for attachment of at least one integrated circuit die, wherein the plurality of rings are formed one inside the other; and forming a plurality of contact points in the die area.Type: GrantFiled: June 30, 2017Date of Patent: November 15, 2022Assignee: Intel CorporationInventors: Nicholas S. Haehn, Edvin Cetegen, Shankar Devasenathipathy
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Publication number: 20210249330Abstract: Embodiments herein relate to systems, techniques, and/or processes directed to a composite thermal matrix structure to provide thermal conductivity within a package. The composite thermal matrix may include a first material that is substantially solid and a second material that is liquid and absorbed into the first material. A package may include the composite thermal matrix within an integrated heat sink coupled with a printed circuit board and encapsulating one or more die where the thermal matrix structure is in a state of compressive stress within the heat sink. The thermal matrix structure may expand and contract as the heat sink warps during thermal cycling to maintain constant thermal conductivity with low stress on the package.Type: ApplicationFiled: February 6, 2020Publication date: August 12, 2021Inventors: Nicholas S. Haehn, Nicholas Neal
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Publication number: 20210242107Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.Type: ApplicationFiled: February 4, 2020Publication date: August 5, 2021Inventors: Wei LI, Edvin CETEGEN, Nicholas S. HAEHN, Mitul MODI, Nicholas NEAL
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Publication number: 20210195798Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Inventors: Nicholas NEAL, Nicholas S. HAEHN, Je-Young CHANG, Kyle ARRINGTON, Aaron MCCANN, Edvin CETEGEN, Ravindranath V. MAHAJAN, Robert L. SANKMAN, Ken P. HACKENBERG, Sergio A. CHAN ARGUEDAS
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Publication number: 20210104490Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.Type: ApplicationFiled: October 8, 2019Publication date: April 8, 2021Inventors: Wei LI, Edvin CETEGEN, Nicholas S. HAEHN, Ram S. VISWANATH, Nicholas NEAL, Mitul MODI
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Publication number: 20210066162Abstract: A device is disclosed. The device includes a substrate, a die on the substrate, a thermal interface material (TIM) on the die, and solder bumps on a periphery of a top surface of the substrate. An integrated heat spreader (IHS) is formed on the solder bumps. The IHS covers the TIM.Type: ApplicationFiled: August 30, 2019Publication date: March 4, 2021Inventors: Sergio A. CHAN ARGUEDAS, Nicholas S. HAEHN, Edvin CETEGEN, Nicholas NEAL, Jacob VEHONSKY, Steve S. CHO, Rahul JAIN, Antariksh Rao Pratap SINGH, Tarek A. IBRAHIM, Thomas HEATON, Vipul MEHTA
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Publication number: 20210035921Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.Type: ApplicationFiled: July 30, 2019Publication date: February 4, 2021Inventors: Nicholas NEAL, Nicholas S. HAEHN, Sergio CHAN ARGUEDAS, Edvin CETEGEN, Jacob VEHONSKY, Steve S. CHO, Rahul JAIN, Antariksh Rao Pratap SINGH, Tarek A. IBRAHIM, Thomas HEATON
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Publication number: 20210020531Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.Type: ApplicationFiled: July 15, 2019Publication date: January 21, 2021Inventors: Edvin CETEGEN, Jacob VEHONSKY, Nicholas S. HAEHN, Thomas HEATON, Steve S. CHO, Rahul JAIN, Tarek IBRAHIM, Antariksh Rao Pratap SINGH, Nicholas NEAL, Sergio CHAN ARGUEDAS, Vipul MEHTA
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Publication number: 20210020532Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.Type: ApplicationFiled: July 15, 2019Publication date: January 21, 2021Inventors: Jacob VEHONSKY, Nicholas S. HAEHN, Thomas HEATON, Steve S. CHO, Rahul JAIN, Tarek IBRAHIM, Antariksh Rao Pratap SINGH, Edvin CETEGEN, Nicholas NEAL, Sergio CHAN ARGUEDAS