Abstract: A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.

Abstract: Methods and apparatus are disclosed to control power consumption within a processor. An example apparatus disclosed herein includes logic to identify at least one instruction type and to initialize a counter value corresponding to a maximum number of instructions to be performed, the maximum number being at least partially dependent upon the identified at least one instruction type. The example apparatus also includes processing logic to be enabled or disabled based, at least in part, on the counter value.

Abstract: Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance.

Abstract: Method, apparatus and system embodiments provide one or more secondary register files to store register values for inactive virtual software threads in a virtual multithreading environment. A separate secondary register file may maintain logical register values for each inactive virtual thread.

Abstract: A buffer virtualization mechanism to allow for a large number of allocate-able buffering resources. In particular, embodiments of the invention involve a tracking technique for implementing the use of virtual buffers within a microprocessor architecture.

Abstract: Method, apparatus and system embodiments provide support for multiple SoEMT software threads on multiple SMT logical thread contexts. A thread translation table maintains physical-to-virtual thread translation information in order to provide such information to structures within a processor that utilize virtual thread information. By associating a thread translation table with such structures, a processor that supports simultaneous multithreading (SMT) may be easily retrofitted to support switch-on-event multithreading on the SMT logical processors.

Abstract: Method, apparatus and system embodiments provide support for multiple SoEMT software threads on multiple SMT logical processors. A thread switch on a given logical processor may be accomplished without interrupting operation of other physical threads. Microarchitectural state for a current virtual thread is “torpedoed” at a torpedo point before a new virtual thread begins operating on the given logical processor. For at least one embodiment, the torpedo mechanism clears microarchitectural state for the current virtual thread, freeing most microarchitectural resources associated with torpedoed instructions. Such mechanism does not interrupt processing of other physical thread(s) and also does not require hardware overhead associated with maintaining in the processor microarchitectural state associated with inactive threads.

Abstract: Methods and apparatus are disclosed to control power consumption within a processor. An example processor disclosed herein comprises an instruction retirement unit; a first set of functional blocks to process a first set of instructions having a first instruction type; a second set of functional blocks to process a second set of instructions having a second instruction type; and a controller to enable the first set of functional blocks to process an instruction allocated to the instruction retirement unit if the type of the instruction is the first type, and to disable the first set of functional blocks after the instruction is retired by the instruction retirement unit.

Abstract: Method, apparatus and system embodiments provide support for multiple SoEMT software threads on multiple SMT logical thread contexts. A sleep state mechanism maintains a current value of an element of architecture state for each physical thread. The current value corresponds to an active virtual thread currently running on the physical thread. The sleep state mechanism also maintains sleep values of the architecture state element for each inactive thread. The active and inactive values may be maintained in a cross-bar configuration. Upon a read of the architecture state element, simplified mux logic selects among the current values to provide the current value for the appropriate active thread. Upon a thread switch, control logic associated with the sleep state mechanism swaps the active state value for the current thread with the inactive state value for the new thread.

Abstract: Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.

Abstract: For use in a processor having a first number of decode units for decoding an ordered stream of floating point instructions, a floating point unit (FPU) for receiving decoded ones of the floating point instructions and a method of processing the decoded ones of the floating point instructions. In one embodiment, the FPU includes: (1) a second number of floating point pipelines that execute the floating point instructions, the second number being at least one and less than the first number, the floating point pipeline having a load unit, an execution core and a store unit, (2) a floating point checkpoint buffer, coupled to the decode units, that queues the decoded ones of the floating point instructions for allocation to the floating point pipelines and (3) a floating point register file, coupled to and cooperable with the floating point checkpoint buffer, that preserves states of the execution core to allow the floating point pipelines to execute the floating point instructions out of order.

Abstract: A method, apparatus, and system are provided for a multi-threaded virtual state mechanism. According to one embodiment, active thread state of a first active thread is received using a virtual state mechanism, and virtual thread state is generated in accordance with the active thread state of the first active thread, and the virtual thread state corresponding to the first active thread is forwarded to state update logic.

Abstract: According to an embodiment of the invention, a method and apparatus for flag value renaming. An embodiment of a method comprises setting a flag for a processor via a first instruction, the first instruction being either a direct update instruction or an indirect update instruction; if the setting of the flag is by a direct update instruction, executing a succeeding second instruction that reads the flag prior to completion of the first instruction; and if the setting of the flag is by an indirect update instruction, delaying the second instruction until after completion of the first instruction.

Abstract: For use in a processor having a first number of decode units for decoding an ordered stream of floating point instructions, a floating point unit (FPU) for receiving decoded ones of the floating point instructions and a method of processing the decoded ones of the floating point instructions. In one embodiment, the FPU includes: (1) a second number of floating point pipelines that execute the floating point instructions, the second number being at least one and less than the first number, the floating point pipeline having a load unit, an execution core and a store unit, (2) a floating point checkpoint buffer, coupled to the decode units, that queues the decoded ones of the floating point instructions for allocation to the floating point pipelines and (3) a floating point register file, coupled to and cooperable with the floating point checkpoint buffer, that preserves states of the execution core to allow the floating point pipelines to execute the floating point instructions out of order.

Abstract: A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.

Abstract: A method and system in a data processing system for managing a hierarchical error diagnostic system having a plurality of diagnostic modules for diagnosing a component failure within a target system having a predetermined group of components within each of a plurality of hierarchical levels. After the identification of selected hierarchical levels within the target system, and identification of the components within each hierarchical level, a first blackboard data storage area is initialized for utilization during a diagnostic session. Thereafter, a diagnostic analysis of a first predetermined group of components within a first selected hierarchical level is initiated. The diagnostic analysis utilizes the first blackboard data storage area and multiple diagnostic modules assigned to diagnose the components within the first selected hierarchical level. Upon conclusion of the diagnostic analysis, a diagnostic result is determined from selected information learned during the first diagnostic analysis.