Abstract: A method for detecting vibration signatures in a reversible drive is disclosed. The method includes the steps of acquiring digital data representative of vibrations in the reversible drive and identifying and grouping together portions of data in a plurality of groups. The identified portions of data relate to a particular direction of travel of the reversible drive and the plurality of groups relate to travel in different directions of the reversible drive. The method can include the further step of processing at least one of the groups of data using signal processing techniques. A system and computer program product for practicing the method for detecting vibration signatures in a reversible drive are also disclosed.

Abstract: A method for detecting vibration signatures in a reversible drive is disclosed. The method includes the steps of acquiring digital data representative of vibrations in the reversible drive and identifying and grouping together portions of data in a plurality of groups. The identified portions of data relate to a particular direction of travel of the reversible drive and the plurality of groups relate to travel in different directions of the reversible drive. The method can include the further step of processing at least one of the groups of data using signal processing techniques. A system and computer program product for practicing the method for detecting vibration signatures in a reversible drive are also disclosed.

Abstract: A programmable optimized-distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable optimized-distribution logic allocator provides an optimized number of product terms to each I/O pin of the CPLDS and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable optimized-distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product-term clusters, to a programmably selected logic macrocell. Specifically, the programmable optimized-distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements.

Abstract: A programmable optimized-distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable optimized-distribution logic allocator provides an optimized number of product terms to each I/O pin of the CPLDS and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable optimized-distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product-term clusters, to a programmably selected logic macrocell. Specifically, the programmable optimized-distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements.

Abstract: An apparatus is provided for removing a coating from a substrate, comprising a nozzle having an outlet and adapted to direct a particle stream therethrough at a predetermined flow rate, a signal source for emitting a signal capable of traversing the particle stream, and a signal sensor positioned to detect the signal emitted by the signal source once the signal has passed through the particle stream. The particle stream is directed from the outlet of the nozzle toward a coating on a substrate to remove the coating from the substrate. Since the signal emitted by the signal source traverses the particle stream before being detected, the intensity of the signal detected by the signal sensor corresponds to a flow rate of the particle stream such that a subsequent change in the intensity of the signal that is detected by the signal sensor indicates a change in the flow rate of the particle stream. A method of monitoring a particle flow in an apparatus used for removing a coating from a substrate is also provided.

Abstract: Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell.

Abstract: A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit includes a block clock generator circuit and a block initialization circuit. The block clock generator circuit receives a first set of product terms in a plurality of product terms and a plurality of clock signals as input signals. In response to the input signals, the block clock generator circuit generates output signals on a plurality of block clock lines. The block initialization circuit receives a second set of product terms in the plurality of product terms as input signals. In response to the input signals, the block initialization circuit generates a plurality of output signals on the block initialization lines.

Abstract: A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix.

Abstract: Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell.

Abstract: Programmable logic device design software is provided for allocating specific resources in a programmable logic device having a multiplicity of programmable logic blocks interconnected by a programmable switch matrix to logic equations in a user logic design. In particular, a resource allocation means for fitting a logic design to a multiplicity of programmable logic blocks with limited interconnectivity between the modules is provided. The resource allocation means requires minimal programmable logic device resources to achieve the allocation of resources within the programmable logic device to the user logic design. The resource allocation means employs block partitioning means and resource assignment means to map user logic to a programmable logic device (PLD) having multiple programmable AND fixed OR arrays interconnected by a programmable switch matrix, i.e., allocate the PLD resources to the user logic.

Abstract: A high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. Further, the switch matrix provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O marcrocells decouple the logic macrocells from the package I/O pins. Thus, the architecture of this invention is easily scalable to higher density devices without compromising speed. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell.

Abstract: An integrated circuit incorporating high voltage semiconductor devices which are controlled by low voltage semiconductor devices is disclosed, including a method for making the same. The low voltage devices which are capable of realizing complex logic functions on the same chip are realized with only one simple extra step in the fabrication process as compared with the process used to fabricate discrete high voltage power transistors. The process addition to implant the low voltage device does not significantly degrade the original capability associated with discrete power transistors. Both laterally developed and vertically developed devices are described. The integrated circuit combines I.sup.2 L logic with power Darlington transistors. A large area ion implantation permits one to fabricate both low and high voltage devices on one substrate. The resulting integrated circuit permits a plurality of loads to be controlled by a simple or complex control function.

Abstract: An integrated circuit incorporating high voltage semiconductor devices which are controlled by low voltage semiconductor devices is disclosed, including a method for making the same. The low voltage devices which are capable of realizing complex logic functions on the same chip are realized with only one simple extra step in the fabrication process as compared with the process used to fabricate discrete high voltage power transistors. The process addition to implant the low voltage device does not significantly degrade the original capability associated with discrete power transistors. Both laterally developed and vertically developed devices are described. The integrated circuit combines I.sup.2 L logic with power Darlington transistors. A large area ion implantation permits one to fabricate both low and high voltage devices on one substrate. The resulting integrated circuit permits a plurality of loads to be controlled by a simple or complex control function.

Abstract: A novel transformer is described for use in a static inverter in association with one or two switching semiconductor devices. The transformer produces an output for control of the associated switching device(s) which changes in sense from conduction aiding to conduction inhibiting as a function of the flux level in the transformer core. The invention is applicable to single loop cores, such as are assembled from two "U" cores. Control is effected by a primary and secondary control winding wound through an aperture pair, the aperture pair being oriented for "neutrality" of the second control winding to the main flux. The aperture pair creates a five branch magnetic path which permits optimizing the control voltage applied to the associated semiconductor devices both to enhance the switching efficiency when the switching device is initially turned on and to reduce stresses on the switching device by precluding transformer saturation when the switching device is turned off.

Abstract: A dc to ac inverter for operating a gaseous discharge lamp through pre-ignition, arc stabilization, warm-up and final run states is disclosed. The arrangement comprises a transformer and a pair of transistors connected for alternate conduction in a self-oscillating configuration in which turn off occurs at a predetermined flux level in each conduction period. The flux limit is used to preclude excess current drain during warm-up when the lamp resistance is at a minimum. A capacitor is provided, resonant at a harmonic of the inverter output waveform for producing the enhanced output voltage required for pre-ignition. The capacitor also helps to maintain a higher harmonic content during warm-up, enhancing the effective ballasting reactance during that period in relation to that during final run operation. A shift of the oscillating frequency of the inverter from pre-ignition to final run operation further enhances inverter operation.