Patents by Inventor Nicholas T. Hendrickson
Nicholas T. Hendrickson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240062816Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.Type: ApplicationFiled: November 3, 2023Publication date: February 22, 2024Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Patent number: 11901000Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.Type: GrantFiled: August 4, 2022Date of Patent: February 13, 2024Assignee: NUMEM INC.Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Publication number: 20240045697Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Patent number: 11829775Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.Type: GrantFiled: July 28, 2022Date of Patent: November 28, 2023Assignee: NUMEM Inc.Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Publication number: 20220382560Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.Type: ApplicationFiled: July 28, 2022Publication date: December 1, 2022Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Publication number: 20220375519Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.Type: ApplicationFiled: August 4, 2022Publication date: November 24, 2022Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Patent number: 11443802Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.Type: GrantFiled: July 9, 2020Date of Patent: September 13, 2022Assignee: NUMEM INC.Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Patent number: 11436025Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.Type: GrantFiled: July 9, 2020Date of Patent: September 6, 2022Assignee: NUMEM INC.Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Publication number: 20220012063Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Applicant: NUMEM Inc.Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Publication number: 20220013169Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Applicant: NUMEM Inc.Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Patent number: 10726880Abstract: An apparatus for storing data in a magnetic random access memory (MRAM) is provided. The MRAM may store data in one or more resistance-based memory cells and may include a plurality of comparators to compare a voltage generated based on the resistance-based memory cells to a reference voltage to determine a stored logic state. In some implementations, the reference voltage may be generated by a plurality resistance-based memory cells. The reference voltage may be adjusted higher or lower by storing different logic states within the resistance-based memory cells.Type: GrantFiled: November 2, 2018Date of Patent: July 28, 2020Assignee: Numem Inc.Inventor: Nicholas T. Hendrickson
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Publication number: 20190130945Abstract: An apparatus for storing data in a magnetic random access memory (MRAM) is provided. The MRAM may store data in one or more resistance-based memory cells and may include a plurality of comparators to compare a voltage generated based on the resistance-based memory cells to a reference voltage to determine a stored logic state. In some implementations, the reference voltage may be generated by a plurality resistance-based memory cells. The reference voltage may be adjusted higher or lower by storing different logic states within the resistance-based memory cells.Type: ApplicationFiled: November 2, 2018Publication date: May 2, 2019Inventor: Nicholas T. Hendrickson
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Patent number: 9646669Abstract: Memory devices, such as MRAM devices, are described that comprise memory elements for storing data and configuration logic for programming memory elements using a two phase boost. The memory devices perform the two phase boosting to program anti-parallel data values during a first programming phase and to program parallel data values during a second programming phase that is subsequent to the first programming phase. The voltage boost is provided by a high percentage of memory elements in a memory device by simultaneously transitioning the source line of the memory elements from a reference voltage to a source voltage during the first programming phase to effectively double the activation voltage for gates of transistors in the memory elements to program anti-parallel data values. Methods are also described for programming memory elements using a two phase boost.Type: GrantFiled: October 15, 2015Date of Patent: May 9, 2017Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventor: Nicholas T. Hendrickson
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Publication number: 20170053687Abstract: Memory devices, such as MRAM devices, are described that comprise memory elements for storing data and configuration logic for programming memory elements using a two phase boost. The memory devices perform the two phase boosting to program anti-parallel data values during a first programming phase and to program parallel data values during a second programming phase that is subsequent to the first programming phase. The voltage boost is provided by a high percentage of memory elements in a memory device by simultaneously transitioning the source line of the memory elements from a reference voltage to a source voltage during the first programming phase to effectively double the activation voltage for gates of transistors in the memory elements to program anti-parallel data values. Methods are also described for programming memory elements using a two phase boost.Type: ApplicationFiled: October 15, 2015Publication date: February 23, 2017Inventor: Nicholas T. Hendrickson
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Patent number: 9373377Abstract: Apparatuses, integrated circuits, and methods are disclosed for testmode security systems. In one such example apparatus, a data storage is configured to store data. A testmode security system is configured to allow a user to access one or more testmodes of the apparatus at least partially responsive to the data storage not storing sensitive data and disallow the user from accessing the one or more testmodes of the apparatus at least partially responsive to the data storage storing sensitive data.Type: GrantFiled: March 14, 2012Date of Patent: June 21, 2016Assignee: Micron Technology, Inc.Inventor: Nicholas T. Hendrickson
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Patent number: 8806263Abstract: Apparatus and methods are disclosed, such as a global timing generator coupled to local control circuits. Each local control circuit can control programming and reading of a memory element in a tile of memory elements in an array responsive to a timing signal(s) from the global timing generator. Additional apparatus and methods are described.Type: GrantFiled: August 26, 2011Date of Patent: August 12, 2014Assignee: Micron Technology, Inc.Inventor: Nicholas T. Hendrickson
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Patent number: 8788868Abstract: Integrated circuits, apparatuses and methods are disclosed, such as a method that includes generating an internal clock signal, receiving an external clock signal, and providing a mixed clock signal at an output. The mixed clock signal has a frequency ranging from a defined maximum frequency of the external clock signal to a frequency margin below a frequency of the internal clock signal. Additional integrated circuits, apparatus and methods are described.Type: GrantFiled: August 23, 2011Date of Patent: July 22, 2014Assignee: Micron Technology, Inc.Inventor: Nicholas T. Hendrickson
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Publication number: 20130125245Abstract: Apparatuses, integrated circuits, and methods are disclosed for testmode security systems. In one such example apparatus, a data storage is configured to store data. A testmode security system is configured to allow a user to access one or more testmodes of the apparatus at least partially responsive to the data storage not storing sensitive data and disallow the user from accessing the one or more testmodes of the apparatus at least partially responsive to the data storage storing sensitive data.Type: ApplicationFiled: March 14, 2012Publication date: May 16, 2013Applicant: Micron Technology, Inc.Inventor: Nicholas T. Hendrickson
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Publication number: 20130055003Abstract: Apparatus and methods are disclosed, such as a global timing generator coupled to local control circuits. Each local control circuit can control programming and reading of a memory element in a tile of memory elements in an array responsive to a timing signal(s) from the global timing generator. Additional apparatus and methods are described.Type: ApplicationFiled: August 26, 2011Publication date: February 28, 2013Applicant: MICRON TECHNOLOGY, INC.Inventor: Nicholas T. Hendrickson
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Publication number: 20130051140Abstract: Integrated circuits, apparatuses and methods are disclosed, such as a method that includes generating an internal clock signal, receiving an external clock signal, and providing a mixed clock signal at an output. The mixed clock signal has a frequency ranging from a defined maximum frequency of the external clock signal to a frequency margin below a frequency of the internal clock signal. Additional integrated circuits, apparatus and methods are described.Type: ApplicationFiled: August 23, 2011Publication date: February 28, 2013Inventor: Nicholas T. Hendrickson