Abstract: A temperature change of a device on an integrated circuit chip due to self-heating and thermal coupling with other device(s) is modeled considering inefficient heat removal from the backside of the chip. To perform such modeling, ratios of an imaginary heat amount to an actual heat amount for different locations on the IC chip must be predetermined using a test integrated circuit (IC) chip. During testing, one test device at one specific location on the test IC chip is selected to function as a heat source, while at least two other test devices at other locations on the test IC chip function as temperature sensors. The heat source is biased and changes in temperature at the heat source and at the sensors are determined. These changes are used to calculate the value of the imaginary heat amount to actual heat amount ratio to be associated with the specific location.

Abstract: A temperature change of a device on an integrated circuit chip due to self-heating and thermal coupling with other device(s) is modeled considering inefficient heat removal from the backside of the chip. To perform such modeling, ratios of an imaginary heat amount to an actual heat amount for different locations on the IC chip must be predetermined using a test integrated circuit (IC) chip. During testing, one test device at one specific location on the test IC chip is selected to function as a heat source, while at least two other test devices at other locations on the test IC chip function as temperature sensors. The heat source is biased and changes in temperature at the heat source and at the sensors are determined. These changes are used to calculate the value of the imaginary heat amount to actual heat amount ratio to be associated with the specific location.

Abstract: A temperature change of a device on an integrated circuit chip due to self-heating and thermal coupling with other device(s) is modeled considering inefficient heat removal from the backside of the chip. To perform such modeling, ratios of an imaginary heat amount to an actual heat amount for different locations on the IC chip must be predetermined using a test integrated circuit (IC) chip. During testing, one test device at one specific location on the test IC chip is selected to function as a heat source, while at least two other test devices at other locations on the test IC chip function as temperature sensors. The heat source is biased and changes in temperature at the heat source and at the sensors are determined. These changes are used to calculate the value of the imaginary heat amount to actual heat amount ratio to be associated with the specific location.

Abstract: A temperature change of a device on an integrated circuit chip due to self-heating and thermal coupling with other device(s) is modeled considering inefficient heat removal from the backside of the chip. To perform such modeling, ratios of an imaginary heat amount to an actual heat amount for different locations on the IC chip must be predetermined using a test integrated circuit (IC) chip. During testing, one test device at one specific location on the test IC chip is selected to function as a heat source, while at least two other test devices at other locations on the test IC chip function as temperature sensors. The heat source is biased and changes in temperature at the heat source and at the sensors are determined. These changes are used to calculate the value of the imaginary heat amount to actual heat amount ratio to be associated with the specific location.

Abstract: A silicon-germanium ESD element comprises a substrate of a first dopant type coupled to a first voltage terminal and a first diode-configured element. The first diode-configured element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, and an emitter of the second dopant type on the SiGe base layer. Preferably, the SiGe base layer ion the collector region is an epitaxial SiGe layer and the second dopant type of the emitter is diffused in to the SiGe base layer. The ESD element of the present invention may further include a second diode-configured element of the same structure as the first diode-configured element, with an isolation region in the substrate separating the first and second diode-configured elements. The first and second diode-configured elements form a diode network.

Abstract: High-performance bipolar transistors with improved wiring options and fabrication methods therefore are set forth. The bipolar transistor includes a base contact structure that has multiple contact pads which permit multiple device layouts when wiring to the transistor. For example, a first device layout may comprise a collector-base-emitter device layout, while a second device layout may comprise a collector-emitter-base device layout. More specifically, the base contact structure at least partially surrounds the emitter and has integral contact pads which extend away from the emitter. Further, sections of the base contact structure are disposed on an insulating layer outside of the perimeter of the base region of the transistor, while other sections directly contact the base region. Specific details of the bipolar transistor, and fabrication methods therefore are also set forth.