Abstract: Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.

Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

Abstract: Substrate-less diode, bipolar and feedthrough integrated circuit structures, and methods of fabricating substrate-less diode, bipolar and feedthrough integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor structure. A plurality of gate structures is over the semiconductor structure. A plurality of P-type epitaxial structures is over the semiconductor structure. A plurality of N-type epitaxial structures is over the semiconductor structure. One or more open locations is between corresponding ones of the plurality of gate structures. A backside contact is connected directly to one of the pluralities of P-type and N-type epitaxial structures.

Abstract: Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

Abstract: Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

Abstract: Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

Abstract: Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

Abstract: Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

Abstract: Embodiments include diode devices and transistor devices. A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts.

Abstract: A system is disclosed for processing billable activities. The system includes a scheduling component configured to support creation of a plurality of activity records. A sub-set of the activity records are designated as being associated with billable activity. The system also includes an accounting component for receiving information based on the sub-set of the activity records. The information is transmitted from the scheduling component to the accounting component.

Abstract: The Cell Phone Wallet Sleeve is a Cell phone sleeve which holds debit and credit cards with your cell phone. The Cell Phone Wallet Sleeve only covers the top part of a flip phone. The Cell Phone Wallet Sleeve has a clear plastic face to allow users to view the cell phone screen and use it's buttons. The screen also protects the phone's screen from getting scratched. The Cell Phone Wallet Sleeve is removable, to be used on it's own as a wallet. The slot for the Bank cards are located behind the screen of the cell phone to keep the cards out of view. This device can be made in different shapes and sizes, to fit any type of cell phone. This device can also be made out of different colors and materials. Some examples include Leather, Nylon, and Polyester. The way to make it would be to stitch the materials together following the details of the drawing provided. All the materials, leather, nylon etc., would be stitched together exactly like a wallet would. The plastic face can be glued or sewn on.

Abstract: A computing device is configured to provide personal information and communications functions. The computing device includes, among other things, a communication interface, a storage device, and a processor. The communication interface is adapted to pass at least one communication. The storage device is operably coupled to the communication interface, and stores a contact information database relative to at least one contact. The storage device also stores auto-association information relative to the at least one contact. The processor is coupled to the storage device and configured to detect an event relative to the communication. The processor analyzes the communication to ascertain communication contact information. A communication history item is automatically generated when the event is detected and the communication contact information corresponds with information in the contact information database that is indicated as auto-associated by the auto-association information.

Abstract: A method and apparatus are provided for determining the layout of a form automatically to accommodate text in the form. Under the method and apparatus, a set of parameters define the sizing and alignment of elements of the form. Sizing and positioning instructions that are separate from the sizing and alignment parameters set the sizing and positioning of elements of the form based on the sizing and alignment parameters. The instructions determine the minimum size for the form, based in part on text in the form. The difference between the minimum size for the form and a desired size for the form is then distributed across the form to size and position the elements in the form.

Abstract: A program interface which provides access from a business management application to an accounting application to share account information. As described in illustrative embodiments, the system includes an interface module to instantiate and invoke an interface from the business management application to generate an accounting record from an opportunity or prospect record in the business management application. Thus, the accounting record is generated through the interface from the business management application to eliminate the need for duplicate data entry in the accounting application.

Abstract: A system is disclosed for processing billable activities. The system includes a scheduling component configured to support creation of a plurality of activity records. A sub-set of the activity records are designated as being associated with billable activity. The system also includes an accounting component for receiving information based on the sub-set of the activity records. The information is transmitted from the scheduling component to the accounting component.