Patents by Inventor Nicholas Van Heel
Nicholas Van Heel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050270058Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.Type: ApplicationFiled: August 9, 2005Publication date: December 8, 2005Inventors: Joseph Sher, David Siek, Huy Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
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Patent number: 6930503Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.Type: GrantFiled: April 30, 2004Date of Patent: August 16, 2005Assignee: Micron Technology, Inc.Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
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Publication number: 20050052218Abstract: Information concerning a condition of a fuse is stored in a latch circuit and may be corrected. A first signal is supplied to the latch circuit which sets the latch circuit in a first state when the fuse is in a first condition and keeps the latch circuit unchanged when the fuse is in a second condition. While the first signal is being supplied, a second signal is supplied to the latch circuit that keeps the latch circuit in the first state when the fuse is in the first condition and sets the latch circuit in a second state when the fuse is in the second condition.Type: ApplicationFiled: September 8, 2003Publication date: March 10, 2005Applicants: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Michael Killian, Nicholas van Heel
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Publication number: 20040201399Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.Type: ApplicationFiled: April 30, 2004Publication date: October 14, 2004Applicant: Micron Technology, Inc.Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
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Patent number: 6756805Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.Type: GrantFiled: November 15, 2002Date of Patent: June 29, 2004Assignee: Micron Technology, Inc.Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
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Publication number: 20030090285Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.Type: ApplicationFiled: November 15, 2002Publication date: May 15, 2003Applicant: Micron Technology, Inc.Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
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Patent number: 6522154Abstract: A method of, and a circuit for, measuring a capacitor gate dielectric thickness. The method includes the step of providing a circuit including a gate dielectric capacitor, and charging the circuit with a known current. A voltage output from said circuit is measured, and this voltage is proportional to the gate dielectric capacitor thickness. The present invention may be effectively employed to obtain a number of important advantages. First, because the supply voltage scales with gate dielectric thickness, chip performance is maximized, even when gate oxide runs thick. Furthermore, oxide reliability is not affected because a constant electric field is guaranteed.Type: GrantFiled: March 16, 2001Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: John Atkinson Fifield, Mark David Jacunski, Thomas Martin Maffitt, Nicholas Van Heel
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Patent number: 6496027Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.Type: GrantFiled: August 21, 1997Date of Patent: December 17, 2002Assignee: Micron Technology, Inc.Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
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Publication number: 20020130672Abstract: A method of, and a circuit for, measuring a capacitor gate dielectric thickness. The method comprises the step of providing a circuit including a gate dielectric capacitor, and charging the circuit with a known current. A voltage output from said circuit is measured, and this voltage is proportional to the gate dielectric capacitor thickness. The present invention may be effectively employed to obtain a number of important advantages. First, because the supply voltage scales with gate dielectric thickness, chip performance is maximized, even when gate oxide runs thick. Furthermore, oxide reliability is not affected because a constant electric field is guaranteed.Type: ApplicationFiled: March 16, 2001Publication date: September 19, 2002Applicant: International Business Machines CorporationInventors: John Atkinson Fifield, Mark David Jacunski, Thomas Martin Maffitt, Nicholas Van Heel