Abstract: Methods and apparatus are provided for processing information items. Processing comprises one of context filtering, context prioritizing, or both context filtering and context prioritizing. In some embodiments the set of context items from which processing criteria are derived includes a user's calendar of appointments, schedule changes, exceptions, and the like.

Abstract: A method and system for dynamically sizing a dedicated memory in a shared memory buffer architecture. At initial boot, system BIOS programs control register to allocate a dedicated memory of a desired size. The size of the dedicated memory allocated is dependent on the performance requirements. If after initial boot, the performance requirements change, it may necessitate a change in dedicated memory size. By reprogramming the control registers, the dedicated memory size is dynamically changed without any manual manipulation of internal components.

Abstract: A method and system for dynamically sizing a dedicated memory in a shared memory buffer architecture. At initial boot, system BIOS programs control register to allocate a dedicated memory of a desired size. The size of the dedicated memory allocated is dependent on the performance requirements. If after initial boot, the performance requirements change, it may necessitate a change in dedicated memory size. By reprogramming the control registers, the dedicated memory size is dynamically changed without any manual manipulation of internal components.

Abstract: A method and system for allowing an arbitrary operating boot in a shared memory buffer architecture system. A chipset including a memory controller, a bridge, and an arbitration unit is used to control access to a shared physical memory. The physical memory is divided between the system memory and dedicated memory to be used by one or more devices. A portion of the physical memory is allocated as a dedicated memory for some system device. The remainder of the memory may be allocated as system memory. The allocation is performed by a system BIOS either at initial start up or through system BIOS calls made during initialization of the device to use the dedicated memory. Programmable bits in the chipset are programmed to prevent the memory controller from claiming dedicated memory accesses during the boot of an operating system. Since the operating system's attempts to write to the dedicated memory are not claimed by the memory controller during memory sizing, they are forwarded to an I/O bus.

Abstract: A method for guaranteeing access to a bus master for reads of main memory in a bridge circuit for joining a host processor, main memory, and a PCI bus, by detecting a read with data posted in the posted write buffer, disabling the posted write buffer, disabling access by the host processor for a selected period, detecting the presence of a retry of the read access, and enabling the posted write buffer after detecting an idle bus for the passage of the preselected time.

Abstract: A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement has an improved method of cache set selection, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical algorithm to predict which way the next occurrence of this branch will go, based upon the history table.