Patents by Inventor Nicholas Wang

Nicholas Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210213683
    Abstract: According to examples, a valve assembly may include a port structure having a plurality of valve ports that each has an input opening. The valve assembly may also include an isolation plate movably mounted to the port structure, the isolation plate having a plurality of openings and an isolation opening. The isolation plate may be movable between a first position in which the plurality of openings is aligned with the input openings of the plurality of valve ports and a second position in which none of the plurality of openings is aligned with an input opening of the plurality of valve ports.
    Type: Application
    Filed: July 21, 2017
    Publication date: July 15, 2021
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Nicholas WANG, Luke P. SOSNOWSKI
  • Publication number: 20210197483
    Abstract: In some examples, an apparatus includes a plurality of conduits to transport a material of a three-dimensional (3D) printing system between locations in the 3D printing system. A sensor assembly detects a clogged condition of a first conduit of the plurality of conduits. A valve assembly connected to the plurality of conduits selectively controls flow of the material through the plurality of conduits, the valve assembly controllable to actuate from a first setting to a second setting responsive to the detected clogged condition.
    Type: Application
    Filed: July 21, 2017
    Publication date: July 1, 2021
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Nicholas WANG
  • Publication number: 20200147886
    Abstract: The technology described herein includes a spreader that creates scattered incidental particles in a build chamber when spreading build material is applied in the build platform. One or more vacuum sources create negative pressure zones in one or more receptacles to collect the incidental particles in the build chamber during printing process and thus minimize the scattering of the incidental particles.
    Type: Application
    Filed: July 31, 2017
    Publication date: May 14, 2020
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Nicholas WANG, Michael CROCKETT, William WINTERS, Arthur H. BARNES, Wesley R. SCHALK, Justin M. ROMAN
  • Publication number: 20190202128
    Abstract: In some examples, a build material recycling system of a three-dimensional (3D) printer can include a build material transport system of the 3D printer, a build material recycling device of the 3D printer that includes a fluidizing membrane and is connected to the build material transport system, and a recycled build material hopper of the 3D printer connected, via the build material
    Type: Application
    Filed: July 20, 2017
    Publication date: July 4, 2019
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Robert Lawrence WINBURNE, Randall West, Nicholas Wang, Luke P. Sosnowski
  • Patent number: 10289418
    Abstract: Techniques are provided for handling a trap encountered in a thread that is part of a thread array that is being executed in a plurality of execution units. In these techniques, a data structure with an identifier associated with the thread is updated to indicate that the trap occurred during the execution of the thread array. Also in these techniques, the execution units execute a trap handling routine that includes a context switch. The execution units perform this context switch for at least one of the execution units as part of the trap handling routine while allowing the remaining execution units to exit the trap handling routine before the context switch. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 14, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Gerald F. Luiz, Philip Alexander Cuadra, Luke Durant, Shirish Gadre, Robert Ohannessian, Lacky V. Shah, Nicholas Wang, Arthur Danskin
  • Patent number: 10235208
    Abstract: A streaming multiprocessor (SM) included within a parallel processing unit (PPU) is configured to suspend a thread group executing on the SM and to save the operating state of the suspended thread group. A load-store unit (LSU) within the SM re-maps local memory associated with the thread group to a location in global memory. Subsequently, the SM may re-launch the suspended thread group. The LSU may then perform local memory access operations on behalf of the re-launched thread group with the re-mapped local memory that resides in global memory.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: March 19, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Nicholas Wang, Lacky V. Shah, Gerald F. Luiz, Philip Alexander Cuadra, Luke Durant, Shirish Gadre
  • Patent number: 10114755
    Abstract: A system, method, and computer program product for warming a cache for a task launch is described. The method includes the steps of receiving a task data structure that defines a processing task, extracting information stored in a cache warming field of the task data structure, and, prior to executing the processing task, generating a cache warming instruction that is configured to load one or more entries of a cache storage with data fetched from a memory.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: October 30, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Scott Ricketts, Nicholas Wang, Shirish Gadre, Gentaro Hirota, Robert Ohannessian, Jr.
  • Patent number: 10095542
    Abstract: Techniques are provided for restoring threads within a processing core. The techniques include, for a first thread group included in a plurality of thread groups, executing a context restore routine to restore from a memory a first portion of a context associated with the first thread group, determining whether the first thread group completed an assigned function, and, if the first thread group completed the assigned function, then exiting the context restore routine, or if the first thread group did not complete the assigned function, then executing one or more operations associated with a trap handler routine.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 9, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Gerald F. Luiz, Philip Alexander Cuadra, Luke Durant, Shirish Gadre, Robert Ohannessian, Lacky V. Shah, Nicholas Wang, Arthur Merlin Danskin
  • Publication number: 20180052707
    Abstract: Techniques are provided for restoring threads within a processing core. The techniques include, for a first thread group included in a plurality of thread groups, executing a context restore routine to restore from a memory a first portion of a context associated with the first thread group, determining whether the first thread group completed an assigned function, and, if the first thread group completed the assigned function, then exiting the context restore routine, or if the first thread group did not complete the assigned function, then executing one or more operations associated with a trap handler routine.
    Type: Application
    Filed: October 30, 2017
    Publication date: February 22, 2018
    Inventors: Gerald F. LUIZ, Philip Alexander CUADRA, Luke DURANT, Shirish GADRE, Robert OHANNESSIAN, Lacky V. SHAH, Nicholas Wang, Arthur Merlin DANSKIN
  • Patent number: 9850398
    Abstract: The present invention provides a powder-free polymeric coating comprising a latex polymer, a metal oxide and a cross-linking agent, the latex polymer comprising a diene and an acrylic acid; and a powder-free glove comprising the powderless coating polymer.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: December 26, 2017
    Inventor: Nicholas Wang
  • Patent number: 9804885
    Abstract: Techniques are provided for restoring threads within a processing core. The techniques include, for a first thread group included in a plurality of thread groups, executing a context restore routine to restore from a memory a first portion of a context associated with the first thread group, determining whether the first thread group completed an assigned function, and, if the first thread group completed the assigned function, then exiting the context restore routine, or if the first thread group did not complete the assigned function, then executing one or more operations associated with a trap handler routine.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: October 31, 2017
    Assignee: NVIDIA Corporation
    Inventors: Gerald F. Luiz, Philip Alexander Cuadra, Luke Durant, Shirish Gadre, Robert Ohannessian, Lacky V. Shah, Nicholas Wang, Arthur Merlin Danskin
  • Patent number: 9678897
    Abstract: A streaming multiprocessor in a parallel processing subsystem processes atomic operations for multiple threads in a multi-threaded architecture. The streaming multiprocessor receives a request from a thread in a thread group to acquire access to a memory location in a lock-protected shared memory, and determines whether a address lock in a plurality of address locks is asserted, where the address lock is associated the memory location. If the address lock is asserted, then the streaming multiprocessor refuses the request. Otherwise, the streaming multiprocessor asserts the address lock, asserts a thread group lock in a plurality of thread group locks, where the thread group lock is associated with the thread group, and grants the request. One advantage of the disclosed techniques is that acquired locks are released when a thread is preempted. As a result, a preempted thread that has previously acquired a lock does not retain the lock indefinitely.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: June 13, 2017
    Assignee: NVIDIA Corporation
    Inventors: Nicholas Wang, Shirish Gadre, Robert Ohannessian, Lacky V. Shah, Matthew Brockmeyer, Stewart Glenn Carlton
  • Publication number: 20170010914
    Abstract: Techniques are provided for restoring threads within a processing core. The techniques include, for a first thread group included in a plurality of thread groups, executing a context restore routine to restore from a memory a first portion of a context associated with the first thread group, determining whether the first thread group completed an assigned function, and, if the first thread group completed the assigned function, then exiting the context restore routine, or if the first thread group did not complete the assigned function, then executing one or more operations associated with a trap handler routine.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Inventors: Gerald F. LUIZ, Philip Alexander CUADRA, Luke DURANT, Shirish GADRE, Robert OHANNESSIAN, Lacky V. SHAH, Nicholas Wang, Arthur Merlin DANSKIN
  • Publication number: 20160304738
    Abstract: The present invention provides a powder-free polymeric coating comprising a latex polymer, a metal oxide and a cross-linking agent, the latex polymer comprising a diene and an acrylic acid; and a powder-free glove comprising the powderless coating polymer.
    Type: Application
    Filed: August 14, 2015
    Publication date: October 20, 2016
    Inventor: Nicholas WANG
  • Patent number: 9448837
    Abstract: Techniques are provided for restoring thread groups in a cooperative thread array (CTA) within a processing core. Each thread group in the CTA is launched to execute a context restore routine. Each thread group, executes the context restore routine to restore from a memory a first portion of context associated with the thread group, and determines whether the thread group completed an assigned function prior to executing the context restore routine. If the thread group completed an assigned function prior to executing the context restore routine, then the thread group exits the context restore routine. If the thread group did not complete the assigned function prior to executing the context restore routine, then the thread group executes one or more operations associated with a trap handler routine. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: September 20, 2016
    Assignee: NVIDIA Corporation
    Inventors: Gerald F. Luiz, Philip Alexander Cuadra, Luke Durant, Shirish Gadre, Robert Ohannessian, Lacky V. Shah, Nicholas Wang, Arthur Merlin Danskin
  • Patent number: 9378139
    Abstract: A system, method, and computer program product for low-latency scheduling and launch of memory defined tasks. The method includes the steps of receiving a task metadata data structure to be stored in a memory associated with a processor, transmitting the task metadata data structure to a scheduling unit of the processor, storing the task metadata data structure in a cache unit included in the scheduling unit, and copying the task metadata data structure from the cache unit to the memory.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: June 28, 2016
    Assignee: NVIDIA Corporation
    Inventors: Scott Ricketts, Brian Scott Pharris, Nicholas Wang, Luke David Durant, Philip Alexander Cuadra, Jerome F. Duluk, Jr.
  • Patent number: 9286119
    Abstract: A system, method, and computer program product for management of dynamic task-dependency graphs. The method includes the steps of generating a first task data structure in a memory for a first task, generating a second task data structure in the memory, storing a pointer to the second task data structure in a first output dependence field of the first task data structure, setting a reference counter field of the second task data structure to a threshold value that indicates a number of dependent events associated with the second task, and launching the second task when the reference counter field stores a particular value. The second task data structure is a placeholder for a second task that is dependent on the first task.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: March 15, 2016
    Assignee: NVIDIA Corporation
    Inventors: Igor Sevastiyanov, Brian Matthew Fahs, Nicholas Wang, Scott Ricketts, Luke David Durant, Brian Scott Pharris
  • Patent number: 9256623
    Abstract: A system, method, and computer program product for scheduling tasks associated with continuation thread blocks. The method includes the steps of generating a first task metadata data structure in a memory, generating a second task metadata data structure in the memory, executing a first task corresponding to the first task metadata data structure in a processor, generating state information representing a continuation task related to the first task and storing the state information in the second task metadata data structure, executing the continuation task in the processor after the one or more child tasks have finished execution, and indicating that the first task has logically finished execution once the continuation task has finished execution. The second task metadata data structure is related to the first task metadata data structure, and at least one instruction in the first task causes one or more child tasks to be executed by the processor.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: February 9, 2016
    Assignee: NVIDIA Corporation
    Inventors: Scott Ricketts, Luke David Durant, Brian Scott Pharris, Igor Sevastiyanov, Nicholas Wang
  • Patent number: 9110810
    Abstract: One embodiment of the present invention sets forth an improved way to prefetch instructions in a multi-level cache. Fetch unit initiates a prefetch operation to transfer one of a set of multiple cache lines, based on a function of a pseudorandom number generator and the sector corresponding to the current instruction L1 cache line. The fetch unit selects a prefetch target from the set of multiple cache lines according to some probability function. If the current instruction L1 cache 370 is located within the first sector of the corresponding L1.5 cache line, then the selected prefetch target is located at a sector within the next L1.5 cache line. The result is that the instruction L1 cache hit rate is improved and instruction fetch latency is reduced, even where the processor consumes instructions in the instruction L1 cache at a fast rate.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: August 18, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Nicholas Wang, Jack Hilaire Choquette
  • Publication number: 20140372703
    Abstract: A system, method, and computer program product for warming a cache for a task launch is described. The method includes the steps of receiving a task data structure that defines a processing task, extracting information stored in a cache warming field of the task data structure, and, prior to executing the processing task, generating a cache warming instruction that is configured to load one or more entries of a cache storage with data fetched from a memory.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Scott Ricketts, Nicholas Wang, Shirish Gadre, Gentaro Hirota, Robert Ohannessian, JR.