Abstract: Circuitry for characterising a test impedance of a test load, the test load coupled between a sense node and a first driver node, the circuitry comprising: driver circuitry configured to apply a time-varying test stimulus between the first driver node and a second driver node, the test stimulus varied in step changes at one or more signal events; a reference load coupled between the second driver node and the sense node, the reference load having a programmable impedance; and a first integrator configured to integrate a voltage derived from the sense node to generate a first integrated signal; and measurement circuitry configured to derive one or more characteristics of the test impedance based on the programmable impedance and the first integrated signal.

Abstract: Circuitry for characterising a test impedance of a test load, the test load coupled between a sense node and a first driver node, the circuitry comprising: driver circuitry configured to apply a time-varying test stimulus between the first driver node and a second driver node, the test stimulus varied in step changes at a one or more of signal events; a reference load coupled between the second driver node and the sense node, the reference load having a programmable impedance comprising: a first programmable capacitance; a programmable resistance connected in series with the first programmable capacitance to form a series combination; and a first integrator configured to integrate a sense voltage derived from the sense node to generate a first integrated signal.

Abstract: Circuitry for characterising a test impedance of a test load, the test load coupled between a sense node and a first driver node, the circuitry comprising: driver circuitry configured to apply a time-varying test stimulus between the first driver node and a second driver node, the test stimulus varied in step changes at one or more signal events; a reference load coupled between the second driver node and the sense node, the reference load having a programmable impedance; and a first integrator configured to integrate a voltage derived from the sense node to generate a first integrated signal; and measurement circuitry configured to derive one or more characteristics of the test impedance based on the programmable impedance and the first integrated signal.

Abstract: A method of controlling operation of a field-powered biometric device comprising biometric acquisition circuitry, processing circuitry controllable to transition between a first functional state having a first power consumption and a second functional state having a second power consumption lower than the first power consumption, and power management circuitry. The method comprises the steps of monitoring, by the power management circuitry, a property indicative of a supply voltage to the processing circuitry; controlling, when the monitored property indicates that the supply voltage has fallen to a first threshold voltage, the processing circuitry to transition from the first functional state to the second functional state; and controlling, when the monitored property indicates that the supply voltage has increased to a second threshold voltage higher than the first threshold voltage, the processing circuitry to transition from the second functional state to the first functional state.

Abstract: A method of controlling operation of a field-powered biometric device comprising biometric acquisition circuitry, processing circuitry controllable to transition between a first functional state having a first power consumption and a second functional state having a second power consumption lower than the first power consumption, and power management circuitry. The method comprises the steps of monitoring, by the power management circuitry, a property indicative of a supply voltage to the processing circuitry; controlling, when the monitored property indicates that the supply voltage has fallen to a first threshold voltage, the processing circuitry to transition from the first functional state to the second functional state; and controlling, when the monitored property indicates that the supply voltage has increased to a second threshold voltage higher than the first threshold voltage, the processing circuitry to transition from the second functional state to the first functional state.

Abstract: A phase locked loop has an integral control path, in which digital representations of phase error are added over successive time intervals, and a charge pump circuit is configured to charge or discharge an integrating capacitor according to successive resultant sum values, with a voltage on the integrating capacitor used to control an output frequency of a controlled oscillator in the phase locked loop.

Abstract: An encoder and an encoding method are suitable for use in an optical communication system. A concatenated coding scheme is used, in which the source data are encoded by means of an outer encoder to produce outer encoded data, and the outer encoded data are encoded by means of an inner encoder to produce inner encoded data, which are transmitted over a communications medium, such as an optical fibre. The inner encoder acts to produce inner encoded data in a format which occupies the space occupied one or more (for example, two) frames as defined in a standard, in this case the ITU-T G.709 standard. The inner encoder forms a product code from two sets of codewords, for example Extended Hamming codes. More particularly, at least one of the two sets of codewords is a shortened code, in order that the inner encoded data exactly occupies a plurality of frames as defined in the standard.

Abstract: A switching circuit, for use in soft-decision Extended Hamming Code decoding, allows the detection of pairs of received bits having “low confidence” and whose position-ids SUM to the syndrome of the received code signal, when the occurrence of an even (and non-zero) number of errors is detected.

Abstract: A switching circuit, for use in soft-decision Extended Hamming Code decoding, allows the detection of pairs of received bits having “low confidence” and whose position-ids SUM to the syndrome of the received code signal, when the occurrence of an even (and non-zero) number of errors is detected.

Abstract: A soft-input/soft-output decoder for product codes attempts to define a candidate codeword for each component code in the received data. Depending on the degree of similarity between the candidate codeword and the received component code, an assumption is made about the reliability of the selected candidate code. The received soft-input data is modified, based on the assumed reliability of the selected candidate code.

Abstract: In a Viterbi decoder, a branch metrics unit (51) receives samples and provides a branch metric to a first and second adder (54 and 55) that adds the branch metric to a first and second path metric from a path metrics memory (52). Concurrently, a comparator (56) compares the first and second path metrics and provides a select signal to a multiplexor (58) to select the output of the first or second adder (54 or 55). The selection signal is also provided to a path memory unit (33) which provides a detected symbol sequence. The output of the first or second adder (54 or 55) is selected by the multiplexor (58) and provided to the path metric memory (52) as an updated path metric.

Abstract: A circuit (11) for tracking rapid changes in peak and trough voltages of a data signal includes a peak detector circuit (13) and a trough detector circuit (14) coupled to the input for detecting peaks and troughs in the data signal and providing a peak and trough detect output signals, respectively. A peak level rate of change detector (17) is coupled to the peak detector circuit (13) for detecting a rate of increase in the voltage level of detected peaks and to the trough detector circuit (14) for controlling the trough detector circuit to detect troughs when the voltage level of detected peaks rises rapidly. Similarly, a trough level rate of change detector (18) is coupled to the trough detector circuit (14) for detecting a rate of decrease in the voltage level of detected troughs and to the peak detector circuit (13) for controlling the peak detector circuit (13) to detect peaks when the voltage level of detected troughs falls rapidly.