Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A system and methods are provided whereby a user of a mobile device can adaptively switch the mobile device from speakerphone mode to handset mode without needing to look at the mobile device or without the need to activate a button or key sequence. In a preferred embodiment, modules are provided in the mobile device which allow for the detection of a voice conversation, the sampling of the user's voice and the switching between the two modes of operation. If the user's voice volume is above a certain threshold the mobile device operates in handset mode. If the user's voice volume is below a certain threshold the mobile device operates in handset mode. Through the inclusion of the embodiments described herein, a mobile device can allow a user to safely and quickly switch from one mode of operation to the other without a requirement for additional hardware in the mobile device.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A receiver comprises a first signal acquisition unit for acquiring a first type of signal block formatted according to a first format, the first signal acquisition unit comprising one or more parameter estimation units for estimating from the received signals one or more signal parameters related to acquisition of the first type of signal block, and wherein where the first type of signal block is interleaved with a second type of signal block formatted according to a second format, one or more parameter estimation units are arranged in operation to conduct signal parameter estimation based upon one or more respective properties of the received second type of signal block prior to continuation of the estimation based upon one or more respective properties of the received first type of signal block.

Abstract: In one embodiment, a wind power ramp event nowcasting system includes a wind condition analyzer for detecting a wind power ramp signal; a sensor array, situated in an area relative to a wind farm, the sensor array providing data to the wind condition analyzer; a mesoscale numerical model; a neural network pattern recognizer; and a statistical forecast model, wherein the statistical model receives input from the wind condition analyzer, the mesoscale numerical model, and the neural network pattern recognizer; and the statistical forecast model outputs a time and duration for the wind power ramp event (WPRE) for the wind farm.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R?i[10]=R?i-1[0]?R?i-1[2], and the permutation code forms, with an additional bit, a twelve bit address.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of Ri?[10]=Ri-1?[0]?Ri-1?[2], and the permutation code forms, with an additional bit, a twelve bit address.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols. The data processing apparatus comprises an interleaver operable to perform an odd interleaving process which interleaves the first sets of input data symbols on to the sub-carrier signals of first OFDM symbols and an even interleaving process which interleaves the second sets of input data symbols on to the sub-carrier signals of second OFDM symbols.

Abstract: A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols. The data processing apparatus comprises an interleaver operable to perform an odd interleaving process which interleaves the first sets of input data symbols on to the sub-carrier signals of first OFDM symbols and an even interleaving process which interleaves the second sets of input data symbols on to the sub-carrier signals of second OFDM symbols.

Abstract: A data processor maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processor maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A method and apparatus for provisioning a third party mobile device emulator from desktop provisioning software, the method having the steps of: designating a common file space between the third party mobile device emulator and the desktop provisioning software; writing files to the common file space from one of the third party mobile device emulator and the desktop provisioning software; and reading the files from the other of the third party mobile device emulator and the desktop provisioning software.

Abstract: A communications system comprises a primary wireless network and at least one secondary wireless networks, the primary and secondary wireless networks differing in at least one characteristic, at least one sensor unit comprising a means for sensing a parameter and a node of that secondary network adapted to transmit data relating to the parameter via that secondary network, at least one local data gathering point associated with the at least one secondary wireless network, incorporating a node of that secondary wireless network, a node of the primary network, and a control unit adapted to receive data signals from the at least one sensor unit via the secondary network, construct an outgoing data signal incorporating information from the received data signal, and transmit the outgoing data signal via the primary network, the primary wireless network being a multipoint radio network.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.