Abstract: System and methods for synchronizing redundant processing elements are provided. In certain embodiments, a self-checking pair of system on chips (SoCs) includes a first SoC configured to execute a first plurality of instructions; and a second SoC configured to execute a second plurality of instructions that are approximately identical; wherein the first SoC exchanges a first instruction count with the second SoC, the first instruction count identifying a number of instructions executed by the first SoC; wherein the second SoC exchanges a second instruction count with the first SoC, the second instruction count identifying a number of instructions executed by the second SoC; and wherein the first SoC executes a first single step execution utility to synchronize the first instruction count with the second instruction count and the second SoC executes a second single step execution utility to synchronize the first instruction count with the second instruction count.

Abstract: Systems and methods for a self-checking pair are provided. In certain embodiments a system on chip in a self-checking pair includes a system architecture; a plurality of communication channels configured for communicating data with an external system; and an integrated system on chip logic configured to collect the data communicated through the plurality of communication channels and transmit the data to a second system on chip and handle received data from the second system on chip, wherein the integrated system on chip logic determines whether the data communicated through the plurality of communication channels matches the received data from the second system on chip.

Abstract: A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit.

Abstract: Systems integrated into a single electronic chip are provided for. The systems include a primary shared bus, a secondary shared bus and an embedded dynamic random access memory (eDRAM) including a first port and a second port. The systems also include a primary processor in operable communication with the eDRAM via the first port; and a secondary processor in operable communication with the eDRAM via the secondary bus and the second port, wherein the primary and secondary processors are operating in synchronization.

Abstract: A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to access the at least one shared cache simultaneously with another of the plurality of processor cores. Each processor core is assigned one of a unique application or a unique application task and the multi-core processor is operable to execute a partitioning operating system that temporally and spatially isolates each unique application and each unique application task such that each of the plurality of processor cores does not attempt to write to the same address space of the at least one shared cache at the same time as another of the plurality of processor cores.

Abstract: Methods and apparatus are provided for a Universal functionality Module (UFM). The apparatus comprises a programmable logic device (PLD) configured to be reprogrammed in real time and a means for universally interfacing the PLD with any effectuator device. The UFM loads a startup personality bit stream from a boot memory, which allows it to read a pin configuration associated with a effectuator device. The UFM receives a function personality associated with the pin configuration, writes the function personality to programmable logic device, and initiates the function personality.

Abstract: Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.

Abstract: Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition.

Abstract: Methods and apparatus are provided for a Universal functionality Module (UFM). The apparatus comprises a programmable logic device (PLD) configured to be reprogrammed in real time and a means for universally interfacing the PLD with any effectuator device. The UFM loads a startup personality bit stream from a boot memory, which allows it to read a pin configuration associated with a effectuator device. The UFM receives a function personality associated with the pin configuration, writes the function personality to programmable logic device, and initiates the function personality.

Abstract: A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit.

Abstract: Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.

Abstract: Methods and systems for a scalable self-checking processing platform are described herein. According to one embodiment, during an execution frame, a first processing element executes both a high-criticality application and a first low-criticality application. During that same execution frame, a second processing element executes both the high-criticality application and a second low-criticality application. The high-criticality application output from the first processing element is compared with that from the second processing element before the next execution frame, and a fault occurs when the output does not match. The low-criticality application is not duplicated or compared. This and other embodiments allow high-criticality applications to be appropriated checked while avoiding the over-dedication of resources to low-criticality applications that do not warrant self-checking.

Abstract: A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to access the at least one shared cache simultaneously with another of the plurality of processor cores. Each processor core is assigned one of a unique application or a unique application task and the multi-core processor is operable to execute a partitioning operating system that temporally and spatially isolates each unique application and each unique application task such that each of the plurality of processor cores does not attempt to write to the same address space of the at least one shared cache at the same time as another of the plurality of processor cores.

Abstract: Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition.

Abstract: The present invention is embodied in a system and method for statistically comparing a first set of digital data to at least a second set of digital data and matching the first set of digital data to appropriately corresponding portions of the second set of digital data. The first or the second set of digital data can be transformed during statistical analysis to enhance statistical analysis of the digital data.

Abstract: Apparatus and systems are provided for dual redundant avionics networks wherein a remote data concentrator (RDC) includes, but is not limited to, a line replaceable unit (LRU) input, a first processing lane coupled to the LRU input, a second processing lane coupled to the LRU input, and a processor coupled to the first processing lane and the second processing lane. The first processing lane has a first output. The second processing lane has a second output. The processor has a link coupling the first processing lane with the second processing lane and is configured to route data from at least one of the first output and the second output to an Ethernet. The link is configured to transfer data between the first processing lane and the second processing lane.

Abstract: The present invention is embodied in a system and method for statistically comparing a first set of digital data to at least a second set of digital data and matching the first set of digital data to appropriately corresponding portions of the second set of digital data. The first or the second set of digital data can be transformed during statistical analysis to enhance statistical analysis of the digital data.

Abstract: A transducer for use in a structural health monitoring system includes a single transducer element. The transducer includes a transmit assembly coupled to the single transducer element. This assembly is configured to produce a multi-cycle square wave drive signal for stimulating the transducer. Additionally, a transmit/receive switch coupled to the single transducer element is provided. This assembly is configured to isolate the drive signal from the receive assembly used to sense the electrical signal generated from any received elastic waves.

Abstract: Systems and methods are provided for managing the computational resources of coprocessor(s), such as graphics processor(s), in a computing system. The systems and methods illustrate management of computational resources of coprocessors to facilitate efficient execution of multiple applications in a multitasking environment. By enabling multiple threads of execution to compose command buffers in parallel, submitting those command buffers for scheduling and dispatch by the operating system, and fielding interrupts that notify of completion of command buffers, the system enables multiple applications to efficiently share the computational resources available in the system.

Abstract: A method for verifying the integrity of a structural health management system comprising a plurality of sensors mounted on a structure, a baseline data set for each of the plurality of sensors and a calibration procedure that uses the structure itself as part of the reference standard is disclosed. Initially a baseline data set, including time-of-flight between each of the plurality of sensors and neighboring sensor selected from the plurality of sensors, is established. Before performing the structural health assessment a calibration-in data set for each of the plurality of sensors is collected. The calibration-in data set is compared to the baseline data set for each sensor of the plurality of sensors. If the calibration-in data set and the baseline data set match then a structure characterization is performed. If the calibration-in data set and the baseline data set do not match, an approach to resolving the ambiguity between inoperable sensors versus structural failure is disclosed.