Abstract: In a packet based communication network 10, a key management center 20 is used to distribute cryptographic keys for either a switched virtual circuit or a permanent virtual circuit. The disclosed methods allow the key management center 20 to communicate directly with the data encryption/decryption devices (DE's) 14 even though they operate in a transparent mode (rather than a store and forward mode). This is accomplished by balancing link counters with calls to fictitious addresses and/or use of interrupt packets transferred between the DTE 12 and the DE 14. In permanent virtual circuits, the MAC of the last packet transmitted under the old cryptographic key is exchanged to synchronize the key change.

Abstract: In a packet based communication network 10, a key management center 20 is used to distribute cryptographic keys for either a switched virtual circuit or a permanent virtual circuit. The disclosed methods allow the key management center 20 to communicate directly with the data encryption/decryption devices (DE's) 14 even though they operate in a transparent mode (rather than a store and forward mode). This is accomplished by balancing link counters with calls to fictitious addresses and/or use of interrupt packets transferred between the DTE 12 and the DE 14. In permanent virtual circuits, the MAC of the last packet transmitted under the cold cryptographic key is exchanged to synchronize the key change.

Abstract: A public-key data encryption system employing RSA public-key data encryption including a message encrypter capable of encrypting messages using a non-secret encryption key, a transmitter-receiver coupled to the message encrypter which transmits or receives an encrypted message to or from a remote location, the transmitter-receiver also being coupled to a decrypter capable of decrypting a received encrypted message using a decryption key which is a secret input to the decrypter, and an encryption-decryption key generator, including a microprocessor or other large-scale integrated circuit or circuits formed to generate a sequence of prime numbers beginning with a selected known prime number having a length relatively short with respect to the desired length of the last in the sequence of prime numbers, and which is constructed to form the sequence of prime numbers in the form hP+1 where P is the preceding prime number in the sequence, and to test hP+1 for primality by first determining if hP+1 has a GCD of 1 wi