Abstract: Polyesters having both ?,?-unsaturated groups and moieties containing activated methylene or methine groups, such as those of beta-ketoester and malonate, are curable in the presence of a base catalysts to form crosslinked networks. Formulations based on such polyesters are suitable for use in coatings and cure at temperatures less than 230° C. without the use of isocyanates.

Abstract: A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.

Abstract: A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.

Abstract: A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad.

Abstract: A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad.

Abstract: A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad.

Abstract: A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad.