Abstract: Methods and systems for partitioning a device to optimize power consumption are disclosed and may include partitioning circuitry within an integrated circuit into a plurality of power domains, wherein each of the domains includes different power consumption and handling requirements and a processor. A processor in one of the domains may handle processing of tasks internal to that domain. A processor in the first domain may handle processing of tasks in a second of the domains. The processor in each of the domains may be communicatively coupled to one or more common busses, which may be shared by each of the domains. One domain may be powered in a continuous mode and may include low leakage circuitry. The processors may include general purpose processors. A processor in one domain may control image processing circuitry, which may comprise image sensor pipeline, 3D pipeline and/or video accelerator circuitry.