Abstract: A graphics controller for a color display system having a bistable liquid crystal display (LCD) for displaying a plurality of pixels arranged in a matrix includes a memory device for storing color data and status bits corresponding to each of the pixels, and a generating device for generating voltage data corresponding to the pixels based on the color data and the status bits for each of the pixels. In an exemplary case, the bistable LCD is a Cholesteric LCD. Preferably, the generating device has a first mode of operation in which the data corresponding to the pixels is generated for each corresponding pixel and a second mode of operation in which no data is generated; the generating device switches from the first operating mode to the second operating mode when all of the status bits for all of the pixels are zeros.

Abstract: Reflective chiral nematic liquid crystal material is disposed between a first set of electrodes and a second set of electrodes arranged on opposed sides of the material to define a collection of pixels. Fast updating dynamic drive scheme is implemented by selectively applying an electric field via the electrodes through the pixels in four phases of energization: preparation, selection, evolution, and non-select. Each phase is made up of a series of voltages having varying amplitudes. The voltage waveform is for each phase controlled based on the selection phase to achieve image uniformity. For example, the evolution voltages that are established across adjacent pixels having the same final state have initial amplitudes that are equal for both pixels to increase image uniformity.

Abstract: An operating method for a color display system including an active matrix bistable liquid crystal display (LCD) having a plurality of pixels arranged in a matrix based on color data and status bits corresponding to each of the pixels stored in a memory includes steps for generating voltage data corresponding to the pixels based on the color data and the status bits stored for each of the pixels, converting the voltage data to drive signals suitable for driving the active matrix bistable LCD, and applying the drive signals to the active matrix bistable LCD. In an exemplary embodiment, the active matrix bistable LCD is a Cholesteric LCD. Advantageously, the generating, converting, and applying steps are repeated for a corresponding pixel N times, where N is an integer established by the status bits.

Abstract: A low power color display system includes a memory which, stores color data and status bits corresponding to a plurality of pixels, status logic, which generates the status bits responsive to receipt of color data for a respective one of the pixels, a data generator, which generates voltage data corresponding to the pixels based on the color data and the status bits for each of the pixels, driver circuitry, which generates voltage signals responsive to receipt of the voltage data for each of the pixels, and a bistable liquid crystal display (LCD) having multiple cells arranged in a matrix, each cell corresponding to a pixel, the LCD being responsive to the voltage signals. Preferably, the system also includes a power supply which provides power to the driver circuitry, and a power manager, the latter turning the power supply ON when the data generator is in the first operating mode and turning the power supply OFF when the data generator is in the second operating mode.

Abstract: A graphics controller for a color display system having a bistable liquid crystal display (LCD) for displaying a plurality of pixels arranged in a matrix includes a memory device for storing color data and status bits corresponding to each of the pixels, and a generating device for generating voltage data corresponding to the pixels based on the color data and the status bits for each of the pixels. In an exemplary case, the bistable LCD is a Cholesteric LCD. Preferably, the generating device has a first mode of operation in which the data corresponding to the pixels is generated for each corresponding pixel and a second mode of operation in which no data is generated; the generating device switches from the first operating mode to the second operating mode when all of the status bits for all of the pixels are zeros.