Abstract: A method includes building a firmware image to execute on a bootloader of a system on chip (SoC), the firmware image including first encryption public and private keys, and digitally signing the firmware image with a second encryption private key. The signed firmware image is encrypted with a symmetric encryption key, which in turn is encrypted with a second encryption public key. The encrypted signed firmware image and the encrypted symmetric encryption key are sent to the SoC to cause the SoC to (1) decrypt the encrypted symmetric encryption key to produce the symmetric encryption key using a third encryption private key from a first asymmetric key pair, (2) decrypt the encrypted signed firmware image to produce the signed firmware image using the symmetric encryption key, and (3) verify a digital signature of the signed firmware image using a third encryption public key from a second asymmetric key pair.

Abstract: The present disclosure provides a system for media path security includes an authoring system having a content stream transform and corrupter for corrupting content data and providing decorrupting data, a media container for conveying the corrupted content data and decorrupting data, and a client system having a fix-up component for fixing the corrupted content data in dependence upon the decorrupting data. A client system is also provided as having an input for receiving a media container and a fix-up component for fixing the corrupted content data in dependence upon the decorrupting data.

Abstract: A system and method for coordinating control setting with respect to an automated input/output (I/O) processor. A state machine having a transition algorithm can be configured in association with a storage controller in order to permit multiple entities to safely transmit an I/O request to an I/O device. Specific combinations of control bits associated with a fast path engine can be determined by identifying different modes with respect to the behavior of the fast path engine. Each mode can be assigned as a state with respect to the state machine. An I/O path exception and error condition that can cause transitions between the states can be determined and the transitions can be assigned from one state to another state. A generic logic template can then be configured to govern the transitions with respect to the state machine. The logic can be executed when an event occurs in order to trigger multiple state transition and/or modifications with respect to the hardware control bits of the fast path engine.

Abstract: A system and method for coordinating control setting with respect to an automated input/output (I/O) processor. A state machine having a transition algorithm can be configured in association with a storage controller in order to permit multiple entities to safely transmit an I/O request to an I/O device. Specific combinations of control bits associated with a fast path engine can be determined by identifying different modes with respect to the behavior of the fast path engine. Each mode can be assigned as a state with respect to the state machine. An I/O path exception and error condition that can cause transitions between the states can be determined and the transitions can be assigned from one state to another state. A generic logic template can then be configured to govern the transitions with respect to the state machine. The logic can be executed when an event occurs in order to trigger multiple state transition and/or modifications with respect to the hardware control bits of the fast path engine.

Abstract: Methods and systems use a hardware controller for controlling commands sent to a plurality of target devices. The controller controls queuing of commands according to respective target device allowed queue depths set in hardware circuitry of the controller. Status of each one of the plurality of target devices is monitored also using controller hardware circuitry. The allowed queue depths can be set in the hardware controller circuitry using firmware and can by dynamically adjustable based on the status of the target devices. Hardware circuitry of the controller is also used to control queuing of commands, for each one of the plurality of target devices, according to the queue depth setting for the target device.