Abstract: The voltage applied to an integrated circuit is scaled so as to account for variations in the manufacturing processes, temperature, and the like, and to allow for power/performance optimization of the integrated circuit. The integrated circuit may characterized during a manufacturing test or anytime thereafter. The characterization data, which reflects the performance and power consumption of the integrated circuit, is used to determine an associated processing/speed bin, which in turn, defines the voltage that will be applied to the integrated circuit during normal operation. Optionally, a number of different supply voltages are applied to different circuit blocks disposed in the same integrated circuit. Each such circuit block may have a different characterization data associated with a different supply voltage.

Abstract: A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents the propagation of data, in particular ingress grains, to a given group of egress ports if the data is not selected by any of the egress ports in a given group. While the ingress data disable method partitions ports into groups and saves power by disabling the fanout tree from the root on a port group basis, the egress data disable method saves power on a port group basis by disabling the fanout tree from the tail end in addition to applying the ingress data disable method. The ESS block also includes an grain select block for selecting and storing a given ingress grain for eventual output to an egress port.