Abstract: A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region in a wafer including an epitaxial layer on a substrate. A first, heavily doped drain region and bit line element is formed around the trench on the surface of the well, and a second, lightly-doped drain region is formed proximate to the first drain region and self-aligned to the trench sidewalls. A source region is located beneath the trench, which is filled with polysilicon, above which is gate and further polysilicon forming a transfer wordline. The well region at the trench sidewalls are doped to control the device threshold level, and the device is thereby also located at a wordline/bitline cross-point.