Abstract: A device for ascertaining address values, for example, for an access to a memory unit. The device including an input value memory for the at least temporary storing of at least two input values. The device is designed to ascertain at least temporarily at least one address value based on the at least two input values.

Abstract: A processing unit, in particular, a microcontroller for a control unit, which includes at least one processing core, one primary memory device, and at least one main connection unit for connecting the at least one processing core to the primary memory device, the processing unit including at least two functional units, the processing unit including at least one functional unit designed as a data flow control unit, which is designed to receive input data, to evaluate the input data, and to generate output data as a function of the evaluation.

Abstract: A device for computing data models, in particular comprising the possibility to detect errors occurring during the computation, has at least two processing units, at least one of the at least two processing units being designed to compute a main data model as a function of at least one state of a system, at least one other of the at least two processing units being designed to compute, as a function of this at least one state of the system, an approximation data model associated with the main data model, the main data model comprising at least one property of the system as a first data model, the approximation data model comprising at least the same property of the system approximately as a second data model, a comparator unit being designed to compare a first result of a first computation of the main data model with a second result of a second computation of the approximation data model associated with the main data model, in order to determine information about a deviation between the first result and the s

Abstract: A computation unit having at least one computation core, a primary memory device, and at least one main connecting unit for connecting the at least one computation core to the primary memory device, the computation unit having at least two functional units, at least a first functional unit of the at least two functional units being embodied a) to receive first data from at least one further functional unit of the at least two functional units, and/or b) to transmit second data to at least one further functional unit of the at least two functional units.

Abstract: A device for computing data models, in particular comprising the possibility to detect errors occurring during the computation, has at least two processing units, at least one of the at least two processing units being designed to compute a main data model as a function of at least one state of a system, at least one other of the at least two processing units being designed to compute, as a function of this at least one state of the system, an approximation data model associated with the main data model, the main data model comprising at least one property of the system as a first data model, the approximation data model comprising at least the same property of the system approximately as a second data model, a comparator unit being designed to compare a first result of a first computation of the main data model with a second result of a second computation of the approximation data model associated with the main data model, in order to determine information about a deviation between the first result and the s

Abstract: A processing unit, in particular, a microcontroller for a control unit, which includes at least one processing core, one primary memory device, and at least one main connection unit for connecting the at least one processing core to the primary memory device, the processing unit including at least two functional units, the processing unit including at least one functional unit designed as a data flow control unit, which is designed to receive input data, to evaluate the input data, and to generate output data as a function of the evaluation.

Abstract: A computation unit having at least one computation core, a primary memory device, and at least one main connecting unit for connecting the at least one computation core to the primary memory device, the computation unit having at least two functional units, at least a first functional unit of the at least two functional units being embodied a) to receive first data from at least one further functional unit of the at least two functional units, and/or b) to transmit second data to at least one further functional unit of the at least two functional units.

Abstract: A model calculation unit for calculating a data-based function model in a control unit is provided, the model calculation unit having a processor core which includes: a multiplication unit for carrying out a multiplication on the hardware side; an addition unit for carrying out an addition on the hardware side; an exponential function unit for calculating an exponential function on the hardware side; a memory in the form of a configuration register for storing hyperparameters and node data of the data-based function model to be calculated; and a logic circuit for controlling, on the hardware side, the calculation sequence in the multiplication unit, the addition unit, the exponential function unit and the memory in order to ascertain the data-based function model.

Abstract: A memory protection unit including hardware registers for entering address tables, a configuration memory for storing the address tables, a preconfigured hardware logic for managing the configuration memory, a data connection between the configuration memory and the hardware logic for loading the hardware registers, a first interface for controlling the loading by a computing core, and a second interface for writing to the configuration memory by the computing core.

Abstract: A hardware-configurable logic unit having a plurality of coarse-grain hardware elements and having a control element, the control element being set up to allow a configuration of the coarse-grain hardware elements to be modified.

Abstract: A control device in a vehicle includes a unit for calculating, during operation of the vehicle, on the basis of at least one input variable ascertained during operation, at least one output variable for a control system of functions of the vehicle. The control device performs the calculation of the output variables using a Bayesian regression of training values ascertained, before operation, for the output variable and the input variable.

Abstract: A method for operating a control unit, the control unit including a software-controlled main processing unit, a strictly hardware-based model calculation unit for calculating an algorithm, for carrying out a Bayesian regression method, based on configuration data, and a memory unit, a model memory area being defined in the memory unit to which a configuration register block for providing the configuration data in the model calculation unit is assigned, a calculation start-configuration register being assigned the highest address in the configuration register block into which configuration data are written, the writing into of which starts the calculation in the model calculation unit, the configuration data being written in a memory area of the memory unit from the model memory area into the configuration register block with an incremental copying process, the addresses being copied in the incremental copying process in ascending order.

Abstract: A system of at least two microcontrollers, each of the at least two microcontrollers having a respective hardware interface that is set up for a terminal of a contact connection, and the at least two microcontrollers being functional both when they are coupled by a contact connection in data-transmitting fashion via the hardware interfaces as well as independently. An electronic component, a computing unit, and a method for producing such a system, are also described.

Abstract: A memory protection unit including hardware registers for entering address tables, a configuration memory for storing the address tables, a preconfigured hardware logic for managing the configuration memory, a data connection between the configuration memory and the hardware logic for loading the hardware registers, a first interface for controlling the loading by a computing core, and a second interface for writing to the configuration memory by the computing core.

Abstract: A method for acoustically sensing an area is described. An acoustic transmit pulse is transmitted into the area by an acoustic transducer and a received signal is acquired with the aid of the transducer, in order to receive the transmit pulse reflected back from the area. Within a post-pulse oscillation time of the transducer, which directly follows the emission of the transmit pulse, the actual phase response of the received signal is determined. In the event the actual phase response deviates from a predefined setpoint phase response, an object is detected within the area. Also described is a device for acoustically sensing an area, which is designed to carry out the method.

Abstract: A method and a control unit for controlling the authorization of charging operations of electrically operated vehicles. A control unit is provided between a main terminal and a plurality of electric coupler sockets, which are connected to the control unit via a power line. A vehicle to be charged is connected to one of the electric coupler sockets, and the total charging current, which is conducted from the main terminal to the electric coupler sockets via the control unit, is measured. Charging-current requests are transmitted to the control unit by each of the vehicles connected to the electric coupler sockets, and the total charging current is compared to the sum of the charging currents reported by the vehicles connected to the charging outlets. The charging outlets are switched off if the total charging current exceeds the sum. The connecting of a vehicle to be charged includes transmitting authorization information from the vehicle to the control unit.

Abstract: A model calculation unit for calculating a data-based function model, in particular a Gaussian process model, in a control unit, including: a processor core to carry out a strictly hardware-based calculation of an algorithm for a data-based function model, the data-based function model being calculated using provided calculation data, in particular hyperparameters and node data; and a strictly hardware-based conversion unit to provide the processor core with at least a portion of the calculation data, in particular the provided node data, in a predefined number format.

Abstract: A method for operating a control unit, the control unit including a software-controlled main processing unit, a strictly hardware-based model calculation unit for calculating an algorithm, for carrying out a Bayesian regression method, based on configuration data, and a memory unit, a model memory area being defined in the memory unit to which a configuration register block for providing the configuration data in the model calculation unit is assigned, a calculation start-configuration register being assigned the highest address in the configuration register block into which configuration data are written, the writing into of which starts the calculation in the model calculation unit, the configuration data being written in a memory area of the memory unit from the model memory area into the configuration register block with an incremental copying process, the addresses being copied in the incremental copying process in ascending order.

Abstract: A model calculation unit for calculating a data-based function model in a control unit is provided, the model calculation unit having a processor core which includes: a multiplication unit for carrying out a multiplication on the hardware side; an addition unit for carrying out an addition on the hardware side; an exponential function unit for calculating an exponential function on the hardware side; a memory in the form of a configuration register for storing hyperparameters and node data of the data-based function model to be calculated; and a logic circuit for controlling, on the hardware side, the calculation sequence in the multiplication unit, the addition unit, the exponential function unit and the memory in order to ascertain the data-based function model.

Abstract: A microcontroller having a computing unit and a logic circuit. The microcontroller carries out computations for a regulation or control in a vehicle. The computing unit is connected to the logic circuit, and the logic circuit has an arrangement for computing an exponential function and is configurable.