Patents by Inventor Nico Caspary
Nico Caspary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11242616Abstract: A silicon ingot has opposite ends. A specific resistance, measured along an axis between the opposite ends of the silicon ingot, has at least one point of inflection where a concavity of the specific resistance changes along the axis. According to another embodiment, a silicon ingot has a first ingot part and a second ingot part between opposite ends of the silicon ingot. The first ingot part has a different specific resistance than the second ingot part. In a region of the silicon ingot between the first and second ingot parts, the specific resistance has at least one point of inflection where a concavity of the specific resistance changes.Type: GrantFiled: April 13, 2018Date of Patent: February 8, 2022Assignee: Infineon Technologies AGInventors: Nico Caspary, Hans-Joachim Schulze
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Patent number: 10957767Abstract: A method of manufacturing is provided that includes providing an n-type silicon wafer, the n-type silicon wafer including n-type dopants partially compensated 20% to 80% by p-type dopants, where a net n-type doping concentration of the n-type silicon wafer is in a range from 1×1013 cm?3 to 1×1015 cm?3; forming hydrogen related donors in the n-type silicon wafer by irradiating the n-type silicon wafer with protons; and annealing the n-type silicon wafer after forming the hydrogen related donors.Type: GrantFiled: January 27, 2020Date of Patent: March 23, 2021Inventors: Nico Caspary, Helmut Oefner, Hans-Joachim Schulze
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Patent number: 10910475Abstract: A method of manufacturing a silicon wafer includes extracting an n-type silicon ingot over an extraction time period from a silicon melt comprising n-type dopants, adding p-type dopants to the silicon melt over at least part of the extraction time period, so as to compensate an n-type doping in the n-type silicon ingot by 20% to 80%, and slicing the silicon ingot.Type: GrantFiled: June 22, 2016Date of Patent: February 2, 2021Assignee: Infineon Technologies AGInventors: Nico Caspary, Hans-Joachim Schulze
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Patent number: 10724148Abstract: A method of Czochralski growth of a silicon ingot includes melting a mixture of silicon material and an n-type dopant material in a crucible. The silicon ingot is extracted from the molten silicon over an extraction time period. Boron is added to the molten silicon over at least part of the extraction time period.Type: GrantFiled: January 21, 2014Date of Patent: July 28, 2020Assignee: Infineon Technologies AGInventors: Nico Caspary, Hans-Joachim Schulze
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Publication number: 20200161424Abstract: A method of manufacturing is provided that includes providing an n-type silicon wafer, the n-type silicon wafer including n-type dopants partially compensated 20% to 80% by p-type dopants, where a net n-type doping concentration of the n-type silicon wafer is in a range from 1×1013 cm?3 to 1×1015 cm?3; forming hydrogen related donors in the n-type silicon wafer by irradiating the n-type silicon wafer with protons; and annealing the n-type silicon wafer after forming the hydrogen related donors.Type: ApplicationFiled: January 27, 2020Publication date: May 21, 2020Applicant: Infineon Technologies AGInventors: Nico CASPARY, Helmut OEFNER, Hans-Joachim SCHULZE
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Patent number: 10566424Abstract: A method of manufacturing a silicon wafer is provided that includes extracting an n-type silicon ingot over an extraction time period from the a silicon melt comprising n-type dopants; adding p-type dopants to the silicon melt over at least part of the extraction time period, thereby compensating an n-type doping in the n-type silicon ingot by 10% to 80%; slicing the silicon ingot; forming hydrogen related donors in the silicon wafer by irradiating the silicon wafer with protons; and annealing the silicon wafer subsequent to the forming of the hydrogen related donors in the silicon wafer.Type: GrantFiled: November 22, 2017Date of Patent: February 18, 2020Assignee: Infineon Technologies AGInventors: Nico Caspary, Helmut Oefner, Hans-Joachim Schulze
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Patent number: 10337117Abstract: A method of Czochralski growth of a silicon ingot includes melting a mixture of silicon material and an n-type dopant material in a crucible. The silicon ingot is extracted from the molten silicon during an extraction time period. The silicon ingot is doped with additional n-type dopant material during at least one sub-period of the extraction time period.Type: GrantFiled: November 7, 2014Date of Patent: July 2, 2019Assignee: Infineon Technologies AGInventors: Nico Caspary, Hans-Joachim Schulze
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Publication number: 20180230622Abstract: A silicon ingot has opposite ends. A specific resistance, measured along an axis between the opposite ends of the silicon ingot, has at least one point of inflection where a concavity of the specific resistance changes along the axis. According to another embodiment, a silicon ingot has a first ingot part and a second ingot part between opposite ends of the silicon ingot. The first ingot part has a different specific resistance than the second ingot part. In a region of the silicon ingot between the first and second ingot parts, the specific resistance has at least one point of inflection where a concavity of the specific resistance changes.Type: ApplicationFiled: April 13, 2018Publication date: August 16, 2018Inventors: Nico Caspary, Hans-Joachim Schulze
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Patent number: 10014400Abstract: A semiconductor device includes: a semiconductor substrate having a first side, a second side opposite the first side, and a thickness; at least one semiconductor component integrated in the semiconductor substrate; a first metallization at the first side of the semiconductor substrate; and a second metallization at the second side of the semiconductor substrate. The semiconductor substrate has an oxygen concentration along a thickness line of the semiconductor substrate which has a global maximum at a position of 20% to 80% of the thickness relative to the first side. The global maximum is at least 2-times larger than the oxygen concentrations at each of the first side and the second side of the semiconductor substrate.Type: GrantFiled: July 14, 2017Date of Patent: July 3, 2018Assignee: Infineon Technologies AGInventors: Helmut Oefner, Nico Caspary, Mohammad Momeni, Reinhard Ploss, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
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Publication number: 20180097064Abstract: A method of manufacturing a silicon wafer is provided that includes extracting an n-type silicon ingot over an extraction time period from the a silicon melt comprising n-type dopants; adding p-type dopants to the silicon melt over at least part of the extraction time period, thereby compensating an n-type doping in the n-type silicon ingot by 10% to 80%; slicing the silicon ingot; forming hydrogen related donors in the silicon wafer by irradiating the silicon wafer with protons; and annealing the silicon wafer subsequent to the forming of the hydrogen related donors in the silicon wafer.Type: ApplicationFiled: November 22, 2017Publication date: April 5, 2018Applicant: Infineon Technologies AGInventors: Nico CASPARY, Helmut OEFNER, Hans-Joachim SCHULZE
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Publication number: 20170316929Abstract: A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.Type: ApplicationFiled: July 14, 2017Publication date: November 2, 2017Inventors: Helmut Oefner, Nico Caspary, Mohammad Momeni, Reinhard Ploss, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
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Patent number: 9786748Abstract: A CZ silicon ingot is doped with donors and acceptors and includes an axial gradient of doping concentration of the donors and of the acceptors. An electrically active net doping concentration, which is based on a difference between the doping concentrations of the donors and acceptors varies by less than 60% for at least 40% of an axial length of the CZ silicon ingot due to partial compensation of at least 20% of the doping concentration of the donors by the acceptors.Type: GrantFiled: May 27, 2015Date of Patent: October 10, 2017Assignee: Infineon Technologies AGInventors: Nico Caspary, Hans-Joachim Schulze
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Patent number: 9728395Abstract: A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.Type: GrantFiled: September 28, 2015Date of Patent: August 8, 2017Assignee: Infineon Technologies AGInventors: Helmut Oefner, Nico Caspary, Mohammad Momeni, Reinhard Ploss, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
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Publication number: 20170062568Abstract: A semiconductor device is provided that includes a silicon semiconductor body having a drift or base zone of net n-type doping. An n-type doping is partially compensated by 10% to 80% with p-type dopants. A net n-type doping concentration in the drift or base zone is in a range from 1×1013 cm?3 to 1×1015 cm?3. A portion of 5% to 75% of the n-type doping is made up of hydrogen related donors.Type: ApplicationFiled: August 25, 2016Publication date: March 2, 2017Applicant: Infineon Technologies AGInventors: Nico CASPARY, Helmut OEFNER, Hans-Joachim SCHULZE
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Publication number: 20160305040Abstract: A method of manufacturing a silicon wafer includes extracting an n-type silicon ingot over an extraction time period from a silicon melt comprising n-type dopants, adding p-type dopants to the silicon melt over at least part of the extraction time period, so as to compensate an n-type doping in the n-type silicon ingot by 20% to 80%, and slicing the silicon ingot.Type: ApplicationFiled: June 22, 2016Publication date: October 20, 2016Inventors: Nico Caspary, Hans-Joachim Schulze
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Publication number: 20160130722Abstract: A method of Czochralski growth of a silicon ingot includes melting a mixture of silicon material and an n-type dopant material in a crucible. The silicon ingot is extracted from the molten silicon during an extraction time period. The silicon ingot is doped with additional n-type dopant material during at least one sub-period of the extraction time period.Type: ApplicationFiled: November 7, 2014Publication date: May 12, 2016Inventors: Nico Caspary, Hans-Joachim Schulze
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Publication number: 20160104622Abstract: A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.Type: ApplicationFiled: September 28, 2015Publication date: April 14, 2016Applicant: INFINEON TECHNOLOGIES AGInventors: Helmut Oefner, Nico Caspary, Mohammad Momeni, Reinhard Ploss, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
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Publication number: 20150349066Abstract: A CZ silicon ingot is doped with donors and acceptors and includes an axial gradient of doping concentration of the donors and of the acceptors. An electrically active net doping concentration, which is based on a difference between the doping concentrations of the donors and acceptors varies by less than 60% for at least 40% of an axial length of the CZ silicon ingot due to partial compensation of at least 20% of the doping concentration of the donors by the acceptors.Type: ApplicationFiled: May 27, 2015Publication date: December 3, 2015Inventors: Nico Caspary, Hans-Joachim Schulze
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Publication number: 20150203988Abstract: A method of Czochralski growth of a silicon ingot includes melting a mixture of silicon material and an n-type dopant material in a crucible. The silicon ingot is extracted from the molten silicon over an extraction time period. Boron is added to the molten silicon over at least part of the extraction time period.Type: ApplicationFiled: January 21, 2014Publication date: July 23, 2015Inventors: Nico Caspary, Hans-Joachim Schulze