Abstract: Polyphased input data is filtered. A number of delay lines are provided corresponding to the number of polyphases. Each delay lines stores a set of input data samples. Filter elements are provided for each delay line. The filter elements operate at a particular time on different subsets of the input data samples stored in the delay line. During a given time interval a number of new input data samples corresponding to the number of filter elements in the group of filter elements are shifted into the delay line. During a plurality of subintervals within the time interval, groups of filter coefficients are supplied to the group of filter elements. In each subinterval, all of the filter elements within the group receive the same set of filter coefficients, and output an output data sample. Output data samples from corresponding filter elements for different delay line are combined to produce filtered data.

Abstract: The present invention is related to a circuit for encoding at least two input symbols by means of a space-time block code, comprising a plurality of multiplexers, each arranged to receive the input symbols and to output a selected symbol, storing means for storing information on which input symbol is to be selected in each multiplexer of the plurality of multiplexers and for storing gain factor information to multiply the multiplexer outputs with, calculation means, coupled with the storing means, for determining an encoded version of the input symbols based on the multiplexer outputs and corresponding gain factors stored in the storing means. The invention further discloses a corresponding circuit for space-time block decoding.

Abstract: The present invention is related to a circuit for encoding at least two input symbols by means of a space-time block code, comprising a plurality of multiplexers, each arranged to receive the input symbols and to output a selected symbol, storing means for storing information on which input symbol is to be selected in each multiplexer of the plurality of multiplexers and for storing gain factor information to multiply the multiplexer outputs with, calculation means, coupled with the storing means, for determining an encoded version of the input symbols based on the multiplexer outputs and corresponding gain factors stored in the storing means. The invention further discloses a corresponding circuit for space-time block decoding.

Abstract: A digital-to-analog conversion system comprises a digital input, a digital-to-analog converter and a modified digital signal generator. The digital-to-analog converter has a conversion frequency and is subject to a periodic error having a periodicity equal to that of an N-th sub-harmonic of the conversion frequency, where N is an integer. The digital input is operable to receive a digital input signal. The modified digital signal generator is interposed between the digital input and the digital-to-analog converter and is operable in response to the digital input signal to generate a modified digital signal. The modified digital signal comprises a dynamic digital mitigation component that mitigates the periodic error of the digital-to-analog converter.

Abstract: A digital-to-analog conversion system comprises a digital input, a digital-to-analog converter and a modified digital signal generator. The digital-to-analog converter has a conversion frequency and is subject to a periodic error having a periodicity equal to that of an N-th sub-harmonic of the conversion frequency, where N is an integer. The digital input is operable to receive a digital input signal. The modified digital signal generator is interposed between the digital input and the digital-to-analog converter and is operable in response to the digital input signal to generate a modified digital signal. The modified digital signal comprises a dynamic digital mitigation component that mitigates the periodic error of the digital-to-analog converter.

Abstract: A communication device for W-CDMA signal transmission and reception has a W-CDMA transmitter having at least one of a first RAM and first registers, wherein the transmitter is configured to operate in accordance with first parameters. Further, the communication device has a W-CDMA receiver having at least one of a second RAM and second registers, wherein the receiver is configured to operate in accordance with second parameters, and signal acquisition component. A processor is in data communication with the W-CDMA transmitter, the W-CDMA receiver and the signal acquisition component, and configured to provide for software configuration of the first and second parameters.

Abstract: A communication device for W-CDMA signal transmission and reception includes a W-CDMA transmitter having at least one of a RAM and registers, a W-CDMA receiver having at least one of a RAM and registers, and a signal acquisition circuit. The communication device is software reconfigurable and further includes a digital circuit for phase unbalance precompensation in the W-CDMA transmitter. The digital circuit includes an input register holding a compensation angle and a section performing arithmetic calculations to acquire a change of an I, Q angle by the compensation angle. A method of operating a W-CDMA communication device includes the acts of configuring the device for a specific use, and performing at least one of transmitting, receiving and acquiring waveform signals. The configuring is preferably done by a processor.

Abstract: The present invention is related to a rake receiver for searching, tracking and combining multipath signals in a spread spectrum transmission, characterised in that it further comprises a plurality of generic fingers (11) arranged to perform any of functions selected from the group consisting of searching, tracking and combining a multipath signal.

Abstract: The present invention is related to a method for positioning fingers of a spread spectrum rake receiver, comprising the steps of:

Abstract: A communication device for W-CDMA signal transmission and reception has a W-CDMA transmitter having at least one of a first RAM and first registers, wherein the transmitter is configured to operate in accordance with first parameters. Further, the communication device has a W-CDMA receiver having at least one of a second RAM and second registers, wherein the receiver is configured to operate in accordance with second parameters, and signal acquisition component. A processor is in data communication with the W-CDMA transmitter, the W-CDMA receiver and the signal acquisition component, and configured to provide for software configuration of the first and second parameters.