Patents by Inventor Nicolò Manaresi

Nicolò Manaresi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040191789
    Abstract: First entities consisting in cells or microorganisms (BIO) and second entities consisting in compounds or compound units, carried typically by microbeads (BEAD), are trapped selectively within closed movable potential cages (S1) by means of dielectrophoretic force generated by mutually opposed electrodes (M1, M2). The cages are set in relative motion so as to bring about the interaction of selected first and second entities, causing the cages containing them to fuse, whereupon results are obtained preferably by reinstating the original cages and/or observing previously empty adjacent cages. The procedure takes place in a device (DE) with two separate chambers (F, FL) connected one to the other by way of a narrow passage (D) and finished with respective selectively controllable inlets and outlets (I1, I2; O1, O2) through which a liquid or semi-liquid buffer (L) can be pumped in or out.
    Type: Application
    Filed: May 3, 2004
    Publication date: September 30, 2004
    Inventors: Nicolo Manaresi, Gianni Medoro, Luigi Altomare, Marco Tartagni, Roberto Guerrieri
  • Publication number: 20020121146
    Abstract: A device for detecting the pressure exerted at different points of a flexible and/or pliable object that may assume different shapes, includes a plurality of capacitive pressure sensors and at least a system for biasing and reading the capacitance of the sensors. The requirements of flexibility or pliability are satisfied by capacitive pressure sensors formed by two orthogonal sets of parallel or substantially parallel electrodes spaced, at least at each crossing between an electrode of one set and an electrode of the other set, by an elastically compressible dielectric, forming an array of pressure sensing pixel capacitors. The system for biasing and reading the capacitance includes column plate electrode selection circuits and row plate electrode selection circuits and a logic circuit for sequentially scanning the pixel capacitors and outputting pixel values of the pressure for reconstructing a distribution map of the pressure over the area of the array.
    Type: Application
    Filed: November 28, 2001
    Publication date: September 5, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Nicolo Manaresi, Marco Tartagni, Joel Monnier, Roberto Guerrieri
  • Publication number: 20020122131
    Abstract: The method is for reading a capacitive sensor and may be implemented by a circuit for biasing and reading capacitances that includes circuits for selecting a column line and a row line, and a charge amplifier producing an output voltage representing the capacitance of the selected capacitor intercepted by the selected column and row lines. The method includes preliminarily resetting the output voltage of the charge amplifier, connecting all the deselected row and column plates of the array to a reference voltage and connecting a feedback capacitor and the selected capacitor to an inverting input of the amplifier, applying a step voltage on the capacitor that is connected to the inverting input of the amplifier, and reading the output voltage at steady-state.
    Type: Application
    Filed: November 26, 2001
    Publication date: September 5, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Maximilian Sergio, Nicolo Manaresi, Marco Tartagni, Roberto Canegallo
  • Patent number: 6301570
    Abstract: The analog processor of this invention is programmable and capable of storing the processing coefficients in analog form. It comprises a storage section having at least one output, plural outputs in most cases, and being adapted to respectively generate programming signals on such outputs; the storage section is input a plurality of supply voltage signals and is operative to produce, in connection with information stored therein, one of the supply voltage signals on each of the outputs, it being understood that one voltage signal may be produced on several such outputs. Advantageously, the processor can also be programmed in a simple manner from circuits of the digital type if switches controlled by storage elements are used in the storage section.
    Type: Grant
    Filed: April 26, 1996
    Date of Patent: October 9, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nicolò Manaresi, Eleonora Franchi, Dario Bruno, Rinaldo Poluzzi
  • Patent number: 6292173
    Abstract: A method of and system for providing user input to a computer captures a first finger position image at a first time and a second finger position image at a second time. The first and second finger position images each comprise a plurality of numerical gray scale values equal to or greater than zero. The system then subtracts the first finger position image from the second finger position image to obtain a composite image. The composite image has a first region comprising numerical values less than zero and a second region comprising numerical values greater than zero. The system provides X-Y input to the computer based upon the relative positions of first and second regions. The system further provides Z input to the computer based upon the relative sizes of said first and second regions.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: September 18, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Rambaldi, Marco Tartagni, Zsolt Miklos Kovaks-Vajna, Nicolo' Manaresi
  • Patent number: 6256022
    Abstract: A low-cost semiconductor user input device for controlling the position of a pointer on a display includes a small array of composite sensors. Each composite sensor of the array is adapted to detect movement of a fingerprint feature. The user input device moves the pointer based upon the net movement detected by the composite sensors of the array.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: July 3, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nicolo' Manaresi, Roberto Rambaldi, Marco Tartagni, Zsolt Miklos Kovaks-Vajna
  • Patent number: 5952874
    Abstract: A transistor threshold extraction circuit having an output and including a first and a second transistor of the same type each having a control terminal and having essentially the same threshold voltage, the control terminal of the first transistor being connected to a constant potential node, a current mirror having at least one input terminal and one output terminal coupled respectively to said first and second transistors to provide bias currents, a first and a second potential reference, and a voltage divider having an intermediate tap and first and second end terminals. The control terminal of the second transistor is coupled to the intermediate tap and the divider is biased by coupling the first and the second end terminals respectively to the first and second potential references. The output is coupled to one of said end terminals.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: September 14, 1999
    Assignee: Consorzio per la Ricerca sulla Microeletrronica nel Mezzogiorno
    Inventors: Nicolo Manaresi, Eleonora Franchi, Dario Bruno, Biagio Giacalone
  • Patent number: 5918221
    Abstract: The analog processor can carry out processings independently of the operating temperature and process parameters, in a reliable manner and at high performance levels using fairly simple circuitry. To achieve this independence, the processor is basically implemented and integrated with MOS transistors, has both voltage inputs and outputs, and includes a biasing section which supplies voltage bias signals, of which at least one is substantially the sum of a voltage proportional to the threshold voltage of the MOS transistors and a reference voltage. This reference voltage can be extracted from a reference potential which is stable to temperature and process parameters, for example that produced by a bandgap type of generator. A major feature of the processor according to the invention is the linearity of its input-output characteristic relative to that reference voltage.
    Type: Grant
    Filed: April 26, 1996
    Date of Patent: June 29, 1999
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Nicolo Manaresi, Eleonora Franchi, Dario Bruno, Rinaldo Poluzzi
  • Patent number: 5825229
    Abstract: A voltage level shift circuit has a first input receiving a first voltage signal and a second input receiving a second voltage signal. The voltage level shift circuit is structured to generate an output voltage at an output terminal which is equal to a sum of the first and second voltage signals. The first voltage signal may be varied to vary a shift of the second voltage signal.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: October 20, 1998
    Assignee: Co. Ri. M.Me--Consorzio Per la Ricera Sulla Microelectronica Nel Mezzogiorno
    Inventors: Nicolo Manaresi, Eleonora Franchi, Dario Bruno, Biagio Giacalone, Vincenzo Matranga
  • Patent number: 5806051
    Abstract: Analog processor of antecedent parts of fuzzy logic inference rules and comprising a plurality of analog generators of membership function each having an output supplying a value corresponding to a degree of truth complemented to one (.alpha.') of logical assignments of the type (A is A') with the outputs being connected together to form a common circuit node and also connected to a current generator and the processor comprising also a voltage control device inserted between a supply voltage pole and a ground voltage reference and a one-way element connected to the common circuit node and the one-way element having an output producing an overall degree of truth for the antecedent part of the fuzzy rule to be processed.
    Type: Grant
    Filed: October 31, 1995
    Date of Patent: September 8, 1998
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Dario Bruno, Biagio Giacalone, Nicolo Manaresi
  • Patent number: 5672960
    Abstract: A transistor threshold extraction circuit including at least two transistors of the same type each having a control terminal and having essentially a same threshold voltage, each of the two transistors also having first and second main conduction terminals, a current mirror circuit having at least two input-output terminals with the two terminals coupled respectively to the two transistors so as to supply bias currents, a voltage generator connected between the two control terminals, and a feedback path between the control terminals and one of the input-output terminals. An output of the extraction circuit is coupled to one of the control terminals.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: September 30, 1997
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Nicolo Manaresi, Antonio Gnudi, Dario Bruno, Biagio Giacalone