Abstract: In an embodiment, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an Ethernet frame processor, at least one Ethernet port coupled to the Ethernet frame processor, and a hardware synchronization circuit coupled to the Ethernet frame processor and to the at least one Ethernet port, the hardware synchronization circuit including a controller, a local clock, a media-independent peripheral coupled to the controller, and a media-dependent peripheral coupled to the media-independent peripheral, wherein power can be provided to the hardware synchronization circuit independent of the Ethernet frame processor.

Abstract: In an embodiment, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an Ethernet frame processor, at least one Ethernet port coupled to the Ethernet frame processor, and a hardware synchronization circuit coupled to the Ethernet frame processor and to the at least one Ethernet port, the hardware synchronization circuit including a controller, a local clock, a media-independent peripheral coupled to the controller, and a media-dependent peripheral coupled to the media-independent peripheral, wherein power can be provided to the hardware synchronization circuit independent of the Ethernet frame processor.

Abstract: Data packets are received from a plurality of communication nodes within a local Ethernet network, the data packets including a media access control address (“MAC address”) are indicative of a destination and a data packet traffic class. Based upon the traffic class of each data packet, each of the received data packets are assigned in to one of the plurality of queues of a memory circuit. Based upon the MAC address of each data packet, the data packets within at least one of the queues are sorted. Each queue is then serviced and the data packets within are transmitted based upon the sorting.

Abstract: A system and method for monitoring a plurality of data streams is disclosed. At a first processing stage, a first memory area is associated to an element of a plurality of data streams. Upon arrival of a frame associated with one of the plurality of data streams, a second memory area is associated to the arrived frame based on the element. In the second memory area, a data indicating an arrival of the arrived frame is recorded and on a successful recording, the frame is forwarded to a second processing stage. An independent process executes at a preselected time interval to erase contents of the first memory area.

Abstract: Data packets are received from a plurality of communication nodes within a local Ethernet network, the data packets including a media access control address (“MAC address”) are indicative of a destination and a data packet traffic class. Based upon the traffic class of each data packet, each of the received data packets are assigned in to one of the plurality of queues of a memory circuit. Based upon the MAC address of each data packet, the data packets within at least one of the queues are sorted. Each queue is then serviced and the data packets within are transmitted based upon the sorting.

Abstract: A system and method for monitoring a plurality of data streams is disclosed. At a first processing stage, a first memory area is associated to an element of a plurality of data streams. Upon arrival of a frame associated with one of the plurality of data streams, a second memory area is associated to the arrived frame based on the element. In the second memory area, a data indicating an arrival of the arrived frame is recorded and on a successful recording, the frame is forwarded to a second processing stage. An independent process executes at a preselected time interval to erase contents of the first memory area.