Abstract: Representative implementations of devices and techniques provide a spread spectrum clocking signal. In a frequency synthesizer, a sequence of values may be generated and used to modulate a frequency of an input signal to the frequency synthesizer.

Abstract: Phase interpolators are provided where an adjustment current is added to currents from a plurality of switchable current sources, for example to reduce an integrated nonlinearity.

Abstract: Phase interpolators are provided where an adjustment current is added to currents from a plurality of switchable current sources, for example to reduce an integrated nonlinearity.

Abstract: Apparatuses and methods are provided where a predefined voltage may be applied in a feedback circuit of a voltage regulator, the feedback circuit coupling and output terminal with an adjust terminal of the voltage regulator.

Abstract: At least one implementation relates to a method that includes receiving a bias voltage provided by a low-dropout voltage regulator (LDO) error amplifier; supplying a feedback voltage to the LDO error amplifier; supplying a power signal to a load; and providing a control signal to enable or disable the load and enable or disable the LDO error amplifier.

Abstract: Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.

Abstract: This disclosure describes techniques for generating signals that have relatively steep frequency profiles with a phase-locked loop (PLL) circuit architecture. In some examples, the techniques for generating signals that have relatively steep frequency profiles may include modulating an amplitude of a forward path signal in a PLL circuit at a location in a forward circuit path of the PLL circuit based on a control signal. The control signal may have an amplitude profile that is determined based on a target frequency profile to be generated by the PLL circuit. Modulating the forward circuit path of the PLL circuit with a signal that is determined based on a target frequency profile may allow a PLL-based frequency synthesizer to generate signals with relatively steep frequency profiles while still maintaining acceptable levels of phase noise.

Abstract: An oscillator may output phased signals to a phase interpolator which is to generate an adjustable output clock signal having a phase offset relative to at least one of the phased signals received from the oscillator. A divider may then divide the frequency of the output signal generated by the phase interpolator by an integer factor.

Abstract: This disclosure describes techniques for generating signals that have relatively steep frequency profiles with a phase-locked loop (PLL) circuit architecture. In some examples, the techniques for generating signals that have relatively steep frequency profiles may include modulating an amplitude of a forward path signal in a PLL circuit at a location in a forward circuit path of the PLL circuit based on a control signal. The control signal may have an amplitude profile that is determined based on a target frequency profile to be generated by the PLL circuit. Modulating the forward circuit path of the PLL circuit with a signal that is determined based on a target frequency profile may allow a PLL-based frequency synthesizer to generate signals with relatively steep frequency profiles while still maintaining acceptable levels of phase noise.

Abstract: Apparatuses and methods are provided where a predefined voltage may be applied in a feedback circuit of a voltage regulator, the feedback circuit coupling and output terminal with an adjust terminal of the voltage regulator.

Abstract: Representative implementations of devices and techniques provide a spread spectrum clocking signal. In a frequency synthesizer, a sequence of values may be generated and used to modulate a frequency of an input signal to the frequency synthesizer.

Abstract: An oscillator may output phased signals to a phase interpolator which is to generate an adjustable output clock signal having a phase offset relative to at least one of the phased signals received from the oscillator. A divider may then divide the frequency of the output signal generated by the phase interpolator by an integer factor.

Abstract: A method and apparatus for supplying independently switched, regulated power to a plurality of loads is disclosed.

Abstract: Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.

Abstract: A method and apparatus for supplying independently switched, regulated power to a plurality of loads is disclosed.

Abstract: In one implementation, an apparatus includes a first input terminal configured to receive a bias voltage, the bias voltage received from a low-dropout voltage regulator (LDO) error amplifier, and a second input terminal configured to receive a supply voltage; a first output terminal configured to supply a feedback voltage, the feedback voltage supplied to the LDO error amplifier, and a second output terminal configured to supply regulated power to an associated load; a regulating portion configured to regulate power supplied to the associated load; and a switching portion configured to enable or disable the load from receiving the regulated power.

Abstract: In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping.

Abstract: In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping.

Abstract: In an embodiment, a circuit is provided comprising a multi-phase oscillator configured to output a plurality of output signals having the same frequency and different phase offsets. A feedback value is generated based on at least two of said output signals. A reference value is generated based on a reference clock and a predetermined value. The reference value and the feedback value are combined.

Abstract: A method and apparatus for supplying independently switched, regulated power to a plurality of loads is disclosed.