Abstract: An electronic device including a digital circuit to be compensated and a compensation device for compensating PVT variations of this digital circuit. This compensation device is arranged also for controlling the operating speed of the digital circuit and can also be arranged for equalising a rise time and a fall time of a logic gate including the transistors of the digital circuit. The electronic device implements a first loop, allowing to control the operating speed of the digital circuit by exploiting the same voltage at the compensation terminals of the compensation device and at the terminals at the digital circuit and at a critical path replica module allowing to control the threshold voltages of the respective transistors. The electronic device can implement also a second loop allowing to equalise the rise and fall times of a logic gate including the transistors of the digital circuit.

Abstract: An electronic device including a digital circuit to be compensated and a compensation device for compensating PVT variations of this digital circuit. This compensation device is arranged also for controlling the operating speed of the digital circuit and can also be arranged for equalising a rise time and a fall time of a logic gate including the transistors of the digital circuit. The electronic device implements a first loop, allowing to control the operating speed of the digital circuit by exploiting the same voltage at the compensation terminals of the compensation device and at the terminals at the digital circuit and at a critical path replica module allowing to control the threshold voltages of the respective transistors. The electronic device can implement also a second loop allowing to equalise the rise and fall times of a logic gate including the transistors of the digital circuit.

Abstract: The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator configured to generate an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of temperature, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.

Abstract: The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator that generates an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of the temperature signal, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.