Patents by Inventor Nicola Vannucci
Nicola Vannucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8497795Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second pluType: GrantFiled: June 22, 2011Date of Patent: July 30, 2013Assignees: STMicroelectronics S.A., STMicroelectronics Pvt. Ltd., STMicroelectronics (Canada) Inc., STMicroelectronics S.r.l.Inventors: Stéphane Le Tual, Pratap Narayan Singh, Oleksiy Zabroda, Nicola Vannucci
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Publication number: 20120139771Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second pluType: ApplicationFiled: June 22, 2011Publication date: June 7, 2012Applicants: STMicroelectronics S.A., STMicroelectronics S.r.l., STMicroelectronics (Canada) Inc., STMicroelectronics Pvt. Ltd.Inventors: Stéphane Le Tual, Pratap Narayan Singh, Oleksiy Zabroda, Nicola Vannucci
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Patent number: 8120135Abstract: A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The isolation structure isolates the temperature sensor from the cell array, and has an isolation trench, which is arranged between the cell array and the temperature sensor. The distance between the temperature sensor and the active transistor cell that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array.Type: GrantFiled: February 11, 2010Date of Patent: February 21, 2012Assignee: Infineon Technologies AGInventors: Norbert Krischke, Nicola Vannucci, Sven Lanzerstorfer, Thomas Ostermann, Mathias Racki, Markus Zundel
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Publication number: 20100207206Abstract: A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The isolation structure isolates the temperature sensor from the cell array, and has an isolation trench, which is arranged between the cell array and the temperature sensor. The distance between the temperature sensor and the active transistor cell that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array.Type: ApplicationFiled: February 11, 2010Publication date: August 19, 2010Applicant: INFINEON TECHNOLOGIES AGInventors: Norbert Krischke, Nicola Vannucci, Sven Lanzerstorfer, Thomas Ostermann, Mathias Racki, Markus Zundel
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Patent number: 7718505Abstract: The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering the substrate surface and filling the second trench and removing partially the protection material, wherein a lower portion of the second trench remains filled with the protection material.Type: GrantFiled: June 22, 2007Date of Patent: May 18, 2010Assignee: Infineon Technologies Austria AGInventors: Nicola Vannucci, Hubert Maier
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Publication number: 20090032906Abstract: An electro static discharge device includes a semiconductor body. The semiconductor body includes a first surface, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged on the first semiconductor region and a third semiconductor region of the first conductivity type. The third semiconductor region is isolated from the first semiconductor region by the second semiconductor region. A resistor structure is arranged in the semiconductor body and comprises at least one trench structure. The resistor structure is arranged at least in the second semiconductor region and provides a high-resistance electrical connection between a first portion and a second portion of the second semiconductor region.Type: ApplicationFiled: July 30, 2007Publication date: February 5, 2009Applicant: Infineon Technologies Austria AGInventors: Thomas Ostermann, Nicola Vannucci
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Publication number: 20080315303Abstract: The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering the substrate surface and filling the second trench and removing partially the protection material, wherein a lower portion of the second trench remains filled with the protection material.Type: ApplicationFiled: June 22, 2007Publication date: December 25, 2008Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Nicola Vannucci, Hubert Maier
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Patent number: 7419883Abstract: A method for fabricating a semiconductor structure having selective dopant regions in a semiconductor substrate having trenches formed therein I disclosed. In one embodiment, by a dopant source of an auxiliary structure, parts of the semiconductor structure which lie within the trenches are doped by means of a drive-in. In one embodiment, the semiconductor structure is patterned in planar regions outside the trenches and selectively doped by an implantation process.Type: GrantFiled: August 22, 2006Date of Patent: September 2, 2008Assignee: Infineon Technologies Austria AGInventors: Nicola Vannucci, Sven Lanzerstorfer
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Publication number: 20070042550Abstract: A method for fabricating a semiconductor structure having selective dopant regions in a semiconductor substrate having trenches formed therein I disclosed. In one embodiment, by a dopant source of an auxiliary structure, parts of the semiconductor structure which lie within the trenches are doped by means of a drive-in. In one embodiment, the semiconductor structure is patterned in planar regions outside the trenches and selectively doped by an implantation process.Type: ApplicationFiled: August 22, 2006Publication date: February 22, 2007Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Nicola Vannucci, Sven Lanzerstorfer
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Publication number: 20050270869Abstract: A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The isolation structure isolates the temperature sensor from the cell array, and has an isolation trench, which is arranged between the cell array and the temperature sensor. The distance between the temperature sensor and the active transistor cell that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array.Type: ApplicationFiled: May 19, 2005Publication date: December 8, 2005Inventors: Norbert Krischke, Nicola Vannucci, Sven Lanzerstorfer, Thomas Krotscheck, Mathias Racki, Markus Zundel