Abstract: Data is read from a memory matrix (10) with a plurality of bit lines (12). A differential sense amplifier (14) receives a signal derived from a first one of the bit lines (12) on a first input. The differential sense amplifier (14) receives a reference signal from a reference output of a reference circuit (15) to a second input. A second one of the bit lines (12), which is adjacent to the first one of the bit lines (12), is coupled to the reference circuit (15), so that a bit line signal value on the second one of the bit lines (12) affects a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value (12) on the second one of the bit lines (12) on a bit line signal value on the first one of the bit lines (12).

Abstract: A network (100) comprises at least a network device (110) and a further network device (120). The network device (110) comprises means (400) arranged for detecting an event (170), means (410) for receiving a first timestamp (420) of the further network device and means for taking a second timestamp. The network device is arranged for providing a signal (180) in dependence of a counter (450) reaching an end count. The network device comprises synchronization means (440) arranged for synchronizing the signal (180) with a further signal (190) provided by the further network device (120) by adjusting a value of the end count (60) to a modified end count (230), said modified end count being in dependence of the first and second timestamp. After having provided the synchronized signal (180c, 180d) the value of the end count is re-adjusted from the modified end count to its value prior to the adjustment.

Abstract: A system comprises an instruction processor (10), a flash memory device (14a), a flash control circuit (14) and a working memory (16). Instructions of an interrupt program are kept stored in the flash memory device (14a). When the instruction processor (10) receives an interrupt signal, the instruction processor (10) executes loading instructions, to cause the flash control circuit (14) to load said instructions of the interrupt program from the flash memory device (14a) into the working memory (16). The instructions of the interrupt program are subsequently executed with the instruction processor (10) from the working memory (16). Preferably it is tested whether a copy of said instructions of the interrupt program is stored in the working memory (16) at the time of the interrupt. If the copy is found stored, execution of said instructions from the copy is started before completing execution of of access instructions that were in progress at the time of the interrupt.

Abstract: A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from the output signal from the respective one of the memory cells (10). A reference generator circuit (24, 26) forms the reference signal from a sum wherein each respective one of the memory cells (10) of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (10). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal.

Abstract: In an example embodiment, an electronic circuit comprises a memory matrix with rows and columns of memory cells. First row conductors are provided for each of the rows. Second row conductors correspond to pairs of rows, each successive row forming a respective pair with a preceding one of the rows, so that each pair overlaps with one row of the next pair. Column conductors are provided for each of the columns. Each of the memory cells comprises an access transistor, a node and a first and a second resistive memory element. The access transistor has a control electrode coupled to the first row conductor of the row of the memory cell, a main current channel coupled between the column conductor for the column of the memory cell and the node. The first and second the resistive memory element are coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.

Abstract: A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current paths being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400).

Abstract: A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity.

Abstract: A data processing circuit comprises an encoder circuit for encoding a data word, wherein each digit may have any one of three or more digit values. The data word is encoded so that digit counts in the data word satisfy predetermined criteria (the digit counts are counts of the numbers of the digits in the encoded data word that assume respective digit values). The encoder defines at least two digit maps, each digit map defining assignments of each of the available digit values to a respective different output digit value. The encoder selects at least two groups of digits within the input data word. Each group is associated with a respective one of the digit maps, the groups being selected so that when each digit map has been applied selectively to the digits from its associated group, digit counts of the number of times respective digit values occur in the data word will satisfy predetermined criteria.

Abstract: A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.

Abstract: This invention relates to a method, a device, a server and a system of/for peer to peer transfer of content.

Abstract: A data storage and replay device uses measurements of the evolution of performance of the storage medium (typically a flash memory circuit) to predict an error rate of retrieval from a region of the storage medium. The prediction is used as a basis for dynamically selecting an ECC for encoding the data prior to storage of the data. The ECC is selected from a plurality of available ECC's so that a fastest encodable ECC is selected that is predicted to produce no more than a predetermined post-decoding error rate given said information. In this way the speed of transmission of data to the device can be maximized while keeping the error rate below an acceptable level in the predicted future after decoding. On decoding the data, which is typically audio or video data, is decoded and replayed at a predetermined speed.

Abstract: Method for writing a label on a recordable record carrier (1), the record carrier adhering to a predefined, standardized condition with respect to a physical parameter. The method retrieves label information, parameter information on the physical parameter, which parameter information is of a higher precision than the precision of the physical parameter mentioned in the pre-defined, standardized condition (22), and writing the label information on the optical disc using the parameter information (26). The invention further relates to a device for performing the method. Retrieving parameter information on the physical parameter with a higher precision than the precision of the physical parameter mentioned in the pre-defined, standardized condition enables writing such a label without a significant distortion in the label.

Abstract: A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity.

Abstract: A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.

Abstract: The present invention relates to a write controller for a memory with a plurality of non-volatile storage cells, a read controller for a memory with a plurality of nonvolatile storage cells, to a combined write/read controller, to a solid state device comprising a memory with a plurality of non-volatile storage cells, a programmer device for writing a binary code to a non-volatile memory, to a method for writing data comprising at least one input bit to a memory having non-volatile storage cells, and to a method for controlling the integrity of data comprising at least one input bit stored in non-volatile storage cells of a memory. The basic concept of the present invention is to extend information stored in a non-volatile memory by at least one checking bit. The checking bit is allocated to one code bit, or to each of a plurality of code bits.

Abstract: A One Time Programmable (OTP) memory cell (10) comprising a first, metallic layer (12) coated with a second, conductive stable transition compound (14) with an insulating layer (16) there-between. The first and second layers (12, 14) are selected according to the difference in Gibbs Free Energy between them, which dictates the chemical energy that will be generated as a result of an exothermic chemical reaction between the two materials. The materials of the first and second layers (12, 14) are highly thermally stable in themselves but, when a voltage is applied to the cell (10), a localized breakdown of the insulative layer (16) results which creates a hotspot (18) that sets off an exothermic chemical reaction between the first and second layers (12, 14). The exothermic reaction generates sufficient heat (20) to create a short circuit across the cell and therefore reduce the resistance thereof.

Abstract: An apparatus comprises a memory with a matrix (10) with rows and columns of memory cells. A read access circuit (14, 16, 18) executes a read command to read a retrieval unit comprising data from a row of the memory cells from the matrix (10) and to output data from the retrieval unit. A processing circuit (12) coupled to the read access circuit (14, 16, 18) is configured to execute an extra read operation involving issuing the read command, receiving the extra data (24), performing error detection on only the extra data (24), using an error detecting code in which the extra data is coded, conditionally performing error correction on the data from the extra data (24) using data from the retrieval unit including the payload data (22), according to an error correcting code in which the retrieval unit is coded, if the error detection indicates an error in the extra data (24).

Abstract: An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.

Abstract: In order to create a record carrier having a side-channel which cannot be copied with a channel-bit recorder, the record carrier (1) has a modulated spiral. By modulating one or more of the spiral parameters, like the channel bit length or the track pitch, a side-channel is created. If a record carrier having such a side-channel is copied using a channel-bit recorder, the information present in the side-channel is lost. The number of bits to be stored in the modulated spiral can be selected as desired; also the way in which the bits are present can be selected; the bits can e.g. can be stored in different bands (A,B,C,D) present on the record carrier, in which band the spiral parameter modulated can be kept constant.

Abstract: A memory (10) is organized as a matrix rows and columns of memory cell circuits (100) and comprises bit line conductors (12) coupled to rows of the memory cells (100). A sensing circuit (14) is coupled to the bit line conductors (12). The sensing circuit (14) is arranged to form respective data signals, each by comparing a respective signal from a plurality of the bit line conductors (12) with a reference level that is common for the bit line conductors (12). A reference level selection circuit (16) with inputs coupled to the plurality of bit line conductors (12) is arranged to control the reference level. The reference level selection circuit (16) selects the reference level dependent on respective analog signal levels on the plurality of the bit line conductors (12), so that analog signal levels from at least respective ones of the plurality of bit line conductors (12) lie on respective sides of the reference level.