Abstract: Packet data corresponding to a multicast (MC) packet received by a network device is stored in a packet memory. A header of the MC packet is analyzed to determine two or more ports via which the MC packet is to be transmitted. It is determined that two or more pending read requests are to read packet data from a particular memory location in the packet memory. In response to determining that the two or more pending read requests are to read packet data from the particular memory location, the packet data is read a single time from the particular memory location. Respective instances of the packet data read from the particular memory location are provided to respective two or more read client devices for subsequent transmission of the packet data via the two or more ports determined by the packet processor.

Abstract: Packet data corresponding to a multicast (MC) packet received by a network device is stored in a packet memory. A header of the MC packet is analyzed to determine two or more ports via which the MC packet is to be transmitted. It is determined that two or more pending read requests are to read packet data from a particular memory location in the packet memory. In response to determining that the two or more pending read requests are to read packet data from the particular memory location, the packet data is read a single time from the particular memory location. Respective instances of the packet data read from the particular memory location are provided to respective two or more read client devices for subsequent transmission of the packet data via the two or more ports determined by the packet processor.

Abstract: Packet data corresponding to a multicast (MC) packet received by a network device is stored in a packet memory. A header of the MC packet is analyzed to determine two or more ports via which the MC packet is to be transmitted. It is determined that two or more pending read requests are to read packet data from a particular memory location in the packet memory. In response to determining that the two or more pending read requests are to read packet data from the particular memory location, the packet data is read a single time from the particular memory location. Respective instances of the packet data read from the particular memory location are provided to respective two or more read client devices for subsequent transmission of the packet data via the two or more ports determined by the packet processor.

Abstract: A network device is described. The network device includes a plurality of ingress interfaces, a plurality of memory units configured to store packets received at the plurality of ingress interfaces, a first pool of memory access tokens, and one or more integrated circuits that implement a memory controller. The memory access tokens correspond to respective memory units and are distinct within the first pool. The memory controller is configured to selectively assign at least one individual memory access token to the ingress interfaces to govern write access to the memory units. The ingress interfaces write packets to memory units identified by the corresponding assigned memory access tokens. The network controller is configured to reassign a first memory access token from a first ingress interface to a second ingress interface between consecutive write commands from the first ingress interface based on a write access scheme to access non-sequential memory units.

Abstract: Forwarding points in time of a clock over a clock boundary is performed by launching the points in time into a buffer, such as a FIFO, in the first clock domain. The oldest point in time is fed into a FIFO or delay line in the other clock domain, which FIFO or delay line comprises a plurality of received points in time, which are shifted through the FIFO or delay line over time. An estimate of a point in time in the second clock domain is derived from a plurality of the points in time in the delay line/FIFO, such as from a mean value thereof. This point in time may be compensated for a known delay in order for this determined point in time to be identical to or close to an actual point in time of the first clock in the first clock domain.

Abstract: A network device is described. The network device includes a plurality of ingress interfaces, a plurality of memory units configured to store packets received at the plurality of ingress interfaces, a first pool of memory access tokens, and one or more integrated circuits that implement a memory controller. The memory access tokens correspond to respective memory units and are distinct within the first pool. The memory controller is configured to selectively assign at least one individual memory access token to the ingress interfaces to govern write access to the memory units. The ingress interfaces write packets to memory units identified by the corresponding assigned memory access tokens. The network controller is configured to reassign a first memory access token from a first ingress interface to a second ingress interface between consecutive write commands from the first ingress interface based on a write access scheme to access non-sequential memory units.

Abstract: Packet data corresponding to a multicast (MC) packet received by a network device is stored in a packet memory. A header of the MC packet is analyzed to determine two or more ports via which the MC packet is to be transmitted. It is determined that two or more pending read requests are to read packet data from a particular memory location in the packet memory. In response to determining that the two or more pending read requests are to read packet data from the particular memory location, the packet data is read a single time from the particular memory location. Respective instances of the packet data read from the particular memory location are provided to respective two or more read client devices for subsequent transmission of the packet data via the two or more ports determined by the packet processor.

Abstract: Forwarding points in time of a clock over a clock boundary is performed by launching the points in time into a buffer, such as a FIFO, in the first clock domain. The oldest point in time is fed into a FIFO or delay line in the other clock domain, which FIFO or delay line comprises a plurality of received points in time, which are shifted through the FIFO or delay line over time. An estimate of a point in time in the second clock domain is derived from a plurality of the points in time in the delay line/FIFO, such as from a mean value thereof. This point in time may be compensated for a known delay in order for this determined point in time to be identical to or close to an actual point in time of the first clock in the first clock domain.