Patents by Inventor Nicolas A. Jarrige

Nicolas A. Jarrige has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Quiescent current (IDDQ) indication and testing apparatus and methods
    Patent number: 8476917
    Abstract: An embodiment of an electronic device includes a logic circuit, a switching element, and a quiescent current (IDDQ) evaluation circuit. The logic circuit is coupled to a first ground node. The switching element is coupled between the first ground node and a second ground node. The switching element is configurable in an electrically non-conductive state when the electronic device is in an IDDQ evaluation state, and in an electrically conductive state when the electronic device is not in the IDDQ evaluation state. When the electronic device is in the IDDQ evaluation state, the IDDQ evaluation circuit is configured to provide a first output signal when an IDDQ indicating voltage across the first and second ground nodes exceeds a reference voltage. Other embodiments include methods for producing an indication of IDDQ in an electronic device and methods for fabricating an electronic device with the capability of producing an IDDQ indication.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: July 2, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Nicolas A. Jarrige, Ibrahim Shihadeh Kandah
  • QUIESCENT CURRENT (IDDQ) INDICATION AND TESTING APPARATUS AND METHODS
    Publication number: 20110187396
    Abstract: An embodiment of an electronic device includes a logic circuit, a switching element, and a quiescent current (IDDQ) evaluation circuit. The logic circuit is coupled to a first ground node. The switching element is coupled between the first ground node and a second ground node. The switching element is configurable in an electrically non-conductive state when the electronic device is in an IDDQ evaluation state, and in an electrically conductive state when the electronic device is not in the IDDQ evaluation state. When the electronic device is in the IDDQ evaluation state, the IDDQ evaluation circuit is configured to provide a first output signal when an IDDQ indicating voltage across the first and second ground nodes exceeds a reference voltage. Other embodiments include methods for producing an indication of IDDQ in an electronic device and methods for fabricating an electronic device with the capability of producing an IDDQ indication.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 4, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Nicolas A. Jarrige, Ibrahim Shihadeh Kandah