Abstract: A method and system for reducing power supply noise comprising receiving a primary data stream at a data rate. The primary data stream comprises a stream of bits having logical values of either zero or one. Then, splitting the primary data stream to create a first group of lower rate data streams and a second group of lower rate data streams. Processing the second group of lower rate data streams to invert the logic values of the bits of the lower rate data streams to create processed lower rate data streams. The first group of lower rate data streams are combined with the processed lower rate data streams to create a complementary data stream. Then, processing the primary data stream and the complementary data stream concurrently with a data processing system, the concurrent processing reducing noise on the power supply.

Abstract: A system for controlling equalization applied to a received signal comprising an equalizer configured to equalize on a received signal to generate an equalized signal, and a clock recovery module configured to recover a clock signal from the equalized signal or the received signal. A clock adjustment system is configured to receive the clock signal, and at least one control signal, to create a sampling clock signal. A filter is configured to filter the equalized signal to create a filtered signal. A sampling unit samples the filtered signal or the equalized signal such that the output of the sampling unit is provided to a controller. The controller is configured to receive and process the output of the sampling unit to generate a boost signal, and the controller is further configured to provide the boost signal to the equalizer to control the amount of equalization performed by the equalizer.

Abstract: A system for controlling equalization applied to a received signal comprising an equalizer configured to equalize on a received signal to generate an equalized signal, and a clock recovery module configured to recover a clock signal from the equalized signal or the received signal. A clock adjustment system is configured to receive the clock signal, and at least one control signal, to create a sampling clock signal. A filter is configured to filter the equalized signal to create a filtered signal. A sampling unit samples the filtered signal or the equalized signal such that the output of the sampling unit is provided to a controller. The controller is configured to receive and process the output of the sampling unit to generate a boost signal, and the controller is further configured to provide the boost signal to the equalizer to control the amount of equalization performed by the equalizer.

Abstract: A method and system for reducing power supply noise comprising receiving a primary data stream at a data rate. The primary data stream comprises a stream of bits having logical values of either zero or one. Then, splitting the primary data stream to create a first group of lower rate data streams and a second group of lower rate data streams. Processing the second group of lower rate data streams to invert the logic values of the bits of the lower rate data streams to create processed lower rate data streams. The first group of lower rate data streams are combined with the processed lower rate data streams to create a complementary data stream. Then, processing the primary data stream and the complementary data stream concurrently with a data processing system, the concurrent processing reducing noise on the power supply.

Abstract: An integrated system for adaptive equalization and jitter reduction of a video signal that includes an adaptive equalizer and a jitter cleaner located on one integrated circuit within a single package. An adaptive equalizer applies frequency specific signal modification to the received signal. A bit rate detector determines a bit rate of the video signal or the equalized signal. The jitter cleaner couples to the adaptive equalizer output and processes the equalized signal to reduce jitter in the equalized signal. A multiplexer receives the equalized signal and the jitter cleaner output and, responsive to a control signal, outputs either the equalized signal or the jitter cleaner output signal. A status monitor may optionally be included to compare the detected bit rate to a bit rate threshold, and a responsive to the comparing activate or deactivate the jitter cleaner and output either the equalized signal or jitter cleaner output.

Abstract: An integrated system for adaptive equalization and jitter reduction of a video signal that includes an adaptive equalizer and a jitter cleaner located on one integrated circuit within a single package. An adaptive equalizer applies frequency specific signal modification to the received signal. A bit rate detector determines a bit rate of the video signal or the equalized signal. The jitter cleaner couples to the adaptive equalizer output and processes the equalized signal to reduce jitter in the equalized signal. A multiplexer receives the equalized signal and the jitter cleaner output and, responsive to a control signal, outputs either the equalized signal or the jitter cleaner output signal. A status monitor may optionally be included to compare the detected bit rate to a bit rate threshold, and a responsive to the comparing activate or deactivate the jitter cleaner and output either the equalized signal or jitter cleaner output.