Patents by Inventor Nicolas Bernard Grossier
Nicolas Bernard Grossier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11921910Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.Type: GrantFiled: July 27, 2021Date of Patent: March 5, 2024Assignees: STMicroelectronics Application GMBH, STMicroelectronics S.r.l.Inventors: Roberto Colombo, Nicolas Bernard Grossier, Giovanni Disirio
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Patent number: 11749367Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.Type: GrantFiled: January 3, 2022Date of Patent: September 5, 2023Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Vivek Mohan Sharma, Deepak Baranwal, Nicolas Bernard Grossier, Samiksha Agarwal
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Publication number: 20230170006Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.Type: ApplicationFiled: November 18, 2022Publication date: June 1, 2023Inventors: Asif Rashid Zargar, Nicolas Bernard Grossier, Charul Jain, Roberto Colombo
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Publication number: 20220308645Abstract: A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down.Type: ApplicationFiled: March 23, 2022Publication date: September 29, 2022Applicants: STMicroelectronics Application GmbH, STMicroelectronics S.r.l.Inventors: Roberto COLOMBO, Nicolas Bernard GROSSIER
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Patent number: 11360143Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.Type: GrantFiled: October 29, 2020Date of Patent: June 14, 2022Assignees: STMicroelectronics International N.V., STMicroelectronics Application GmbH, STMicroelectronics S.r.l.Inventors: Avneep Kumar Goyal, Deepak Baranwal, Thomas Szurmant, Nicolas Bernard Grossier
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Publication number: 20220137128Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.Type: ApplicationFiled: October 29, 2020Publication date: May 5, 2022Applicants: STMicroelectronics International N.V., STMicroelectronics Application GmbH, STMicroelectronics S.r.l.Inventors: Avneep Kumar GOYAL, Deepak BARANWAL, Thomas SZURMANT, Nicolas Bernard GROSSIER
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Patent number: 11321492Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.Type: GrantFiled: November 30, 2020Date of Patent: May 3, 2022Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS APPLICATION GMBHInventors: Roberto Colombo, Nicolas Bernard Grossier, Giovanni Disirio, Lorenzo Re Fiorentin
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Publication number: 20220122682Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.Type: ApplicationFiled: January 3, 2022Publication date: April 21, 2022Inventors: Vivek Mohan Sharma, Deepak Baranwal, Nicolas Bernard Grossier, Samiksha Agarwal
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Patent number: 11217323Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first memory error packet associated with a first memory; receiving, with the first buffer, a second memory error packet associated with a second memory; transmitting a first reading request for reading the first memory error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central memory error management unit (MEMU); in response to receiving the first reading request, reading the first memory error packet from the first buffer, transmitting the first memory error packet to a controller of the central MEMU, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second memory error packet.Type: GrantFiled: September 2, 2020Date of Patent: January 4, 2022Assignee: STMicroelectronics International N.V.Inventors: Vivek Mohan Sharma, Deepak Baranwal, Nicolas Bernard Grossier, Samiksha Agarwal
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Patent number: 11210161Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.Type: GrantFiled: July 14, 2020Date of Patent: December 28, 2021Assignees: STMicroelectronics Application GMBH, STMicroelectronics S.r.l.Inventors: Roberto Colombo, Nicolas Bernard Grossier, Roberta Vittimani
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Publication number: 20210357538Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.Type: ApplicationFiled: July 27, 2021Publication date: November 18, 2021Inventors: Roberto Colombo, Nicolas Bernard Grossier, Giovanni Disirio
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Patent number: 11093658Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.Type: GrantFiled: May 9, 2018Date of Patent: August 17, 2021Assignees: STMicroelectronics S.r.l., STMicroelectronics Application GMBHInventors: Roberto Colombo, Nicolas Bernard Grossier, Giovanni Disirio
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Publication number: 20210089329Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.Type: ApplicationFiled: November 30, 2020Publication date: March 25, 2021Inventors: Roberto COLOMBO, Nicolas BERNARD GROSSIER, Giovanni DISIRIO, Lorenzo RE FIORENTIN
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Patent number: 10878131Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.Type: GrantFiled: April 27, 2018Date of Patent: December 29, 2020Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS APPLICATION GMBHInventors: Roberto Colombo, Nicolas Bernard Grossier, Giovanni Disirio, Lorenzo Re Fiorentin
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Publication number: 20200341836Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.Type: ApplicationFiled: July 14, 2020Publication date: October 29, 2020Inventors: Roberto Colombo, Nicolas Bernard Grossier, Roberta Vittimani
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Patent number: 10754723Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.Type: GrantFiled: May 9, 2018Date of Patent: August 25, 2020Assignees: STMICROELECTRONICS APPLICATION GMBH, STMICROELECTRONICS S.R.L.Inventors: Roberto Colombo, Nicolas Bernard Grossier, Roberta Vittimani
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Patent number: 10254338Abstract: A semiconductor device, for example an integrated circuit such as a microcontroller (MCU) or a digital signal processor (DSP), includes a semiconductor die coupled with a power supply line, a debug module coupled with the semiconductor die to exchange semiconductor die debug command and data signals with the semiconductor die, and a modem coupled with the power supply line. The debug module is arranged to convey the semiconductor die debug command and data signals over the power supply line.Type: GrantFiled: July 27, 2016Date of Patent: April 9, 2019Assignee: STMICROELECTRONICS S.R.L.Inventors: Nicolas Bernard Grossier, Lorenzo Guerrieri, Giuseppe Livio Gobbato, Daniele Zerbini, Martina Cordoni, Pasqualina Fragneto
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Publication number: 20180330127Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.Type: ApplicationFiled: May 9, 2018Publication date: November 15, 2018Inventors: Roberto Colombo, Nicolas Bernard Grossier, Giovanni Disirio
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Publication number: 20180330123Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.Type: ApplicationFiled: April 27, 2018Publication date: November 15, 2018Inventors: Roberto COLOMBO, Nicolas BERNARD GROSSIER, Giovanni DISIRIO, Lorenzo RE FIORENTIN
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Publication number: 20180329774Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.Type: ApplicationFiled: May 9, 2018Publication date: November 15, 2018Inventors: Roberto Colombo, Nicolas Bernard Grossier, Roberta Vittimani