Patents by Inventor Nicolas Borrel
Nicolas Borrel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11829178Abstract: An embodiment electronic circuit power supply device is configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node; regulate a potential of the node to a constant value by acting on the third current; flow a fourth constant current through a third conductor connected to the node; and consume a fifth current that is an image of the third current.Type: GrantFiled: August 11, 2021Date of Patent: November 28, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Demange, Nicolas Borrel, Jimmy Fort
-
Patent number: 11804842Abstract: A physically unclonable function device includes a set of diode-connected MOS transistors having a random distribution of respective threshold voltages. A first circuit is configured to impose, on each first transistor, a fixed respective gate voltage regardless of the value of a current flowing in this first transistor. A second circuit is configured to impose, on each second transistor, a fixed respective gate voltage regardless of the value of a current flowing in this second transistor. A current mirror stage is coupled between the first circuit and the second circuit and is configured to deliver the reference current from a sum of the currents flowing in the first transistors. A comparator is configured to deliver a signal whose level depends on a comparison between a first current obtained from a reference current based on the first transistors and a second current of the second transistors.Type: GrantFiled: June 22, 2022Date of Patent: October 31, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Borrel, Jimmy Fort, Mathieu Lisart
-
Patent number: 11698651Abstract: The present invention concerns an electronic circuit power supply device, configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node, a first branch of a current mirror conducting the third current; flow a fourth constant current through a third conductor connected to the node; consume a fifth current that is an image of the third current; and regulate a potential of the node by acting on a gate potential of a transistor electrically in series with a second branch of the current mirror.Type: GrantFiled: August 11, 2021Date of Patent: July 11, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Demange, Nicolas Borrel, Jimmy Fort
-
Patent number: 11531049Abstract: An embodiment integrated circuit includes a first electromagnetic pulse detection device that comprises a first loop antenna formed in an interconnection structure of the integrated circuit, a first end of the first antenna being connected to a first node of application of a power supply potential and a second end of the antenna being coupled to a second node of application of the power supply potential, and a first circuit connected to the second end of the first antenna and configured to output a first signal representative of a comparison of a first current in the first antenna with a first threshold.Type: GrantFiled: May 17, 2021Date of Patent: December 20, 2022Assignee: STMicroelectronics (Rousset) SASInventors: Clement Champeix, Mathieu Dumont, Nicolas Borrel, Mathieu Lisart
-
Publication number: 20220321124Abstract: A physically unclonable function device includes a set of diode-connected MOS transistors having a random distribution of respective threshold voltages. A first circuit is configured to impose, on each first transistor, a fixed respective gate voltage regardless of the value of a current flowing in this first transistor. A second circuit is configured to impose, on each second transistor, a fixed respective gate voltage regardless of the value of a current flowing in this second transistor. A current mirror stage is coupled between the first circuit and the second circuit and is configured to deliver the reference current from a sum of the currents flowing in the first transistors. A comparator is configured to deliver a signal whose level depends on a comparison between a first current obtained from a reference current based on the first transistors and a second current of the second transistors.Type: ApplicationFiled: June 22, 2022Publication date: October 6, 2022Inventors: Nicolas Borrel, Jimmy Fort, Mathieu Lisart
-
Patent number: 11374569Abstract: The physically unclonable function device (DIS) comprises a set of MOS transistors (TR1i, TR2j) mounted in diodes having a random distribution of respective threshold voltages, and comprising N first transistors and at least one second transistor. At least one output node of the function is capable of delivering a signal, the level of which depends on the comparison between a current obtained using a current circulating in the at least one second transistor and a current obtained using a reference current that is equal or substantially equal to the average of the currents circulating in the N first transistors. A first means (FM1i) is configured to impose on each first transistor a respective fixed gate voltage regardless of the value of the current circulating in the first transistor, and a second means (SM2j) is configured to impose a respective fixed gate voltage on each second transistor regardless of the value of the current circulating in the second transistor.Type: GrantFiled: November 28, 2019Date of Patent: June 28, 2022Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Borrel, Jimmy Fort, Mathieu Lisart
-
Publication number: 20220066494Abstract: An embodiment electronic circuit power supply device is configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node; regulate a potential of the node to a constant value by acting on the third current; flow a fourth constant current through a third conductor connected to the node; and consume a fifth current that is an image of the third current.Type: ApplicationFiled: August 11, 2021Publication date: March 3, 2022Inventors: Nicolas Demange, Nicolas Borrel, Jimmy Fort
-
Publication number: 20220066488Abstract: The present invention concerns an electronic circuit power supply device, configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node, a first branch of a current mirror conducting the third current; flow a fourth constant current through a third conductor connected to the node; consume a fifth current that is an image of the third current; and regulate a potential of the node by acting on a gate potential of a transistor electrically in series with a second branch of the current mirror.Type: ApplicationFiled: August 11, 2021Publication date: March 3, 2022Inventors: Nicolas Demange, Nicolas Borrel, Jimmy Fort
-
Publication number: 20220052691Abstract: The physically unclonable function device (DIS) comprises a set of MOS transistors (TR1i, TR2j) mounted in diodes having a random distribution of respective threshold voltages, and comprising N first transistors and at least one second transistor. At least one output node of the function is capable of delivering a signal, the level of which depends on the comparison between a current obtained using a current circulating in the at least one second transistor and a current obtained using a reference current that is equal or substantially equal to the average of the currents circulating in the N first transistors. A first means (FM1i) is configured to impose on each first transistor a respective fixed gate voltage regardless of the value of the current circulating in the first transistor, and a second means (SM2j) is configured to impose a respective fixed gate voltage on each second transistor regardless of the value of the current circulating in the second transistor.Type: ApplicationFiled: November 28, 2019Publication date: February 17, 2022Applicant: STMicroelectronics (Rousset) SASInventors: Nicolas Borrel, Jimmy Fort, Mathieu Lisart
-
Publication number: 20210405100Abstract: An embodiment integrated circuit includes a first electromagnetic pulse detection device that comprises a first loop antenna formed in an interconnection structure of the integrated circuit, a first end of the first antenna being connected to a first node of application of a power supply potential and a second end of the antenna being coupled to a second node of application of the power supply potential, and a first circuit connected to the second end of the first antenna and configured to output a first signal representative of a comparison of a first current in the first antenna with a first threshold.Type: ApplicationFiled: May 17, 2021Publication date: December 30, 2021Inventors: Clement Champeix, Mathieu Dumont, Nicolas Borrel, Mathieu Lisart
-
Patent number: 11137786Abstract: An electronic device includes a starting circuit configured to compare a value representative of the power supply voltage with a threshold, wherein the circuit includes a generator of a current proportional to temperature.Type: GrantFiled: May 13, 2020Date of Patent: October 5, 2021Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Jimmy Fort, Maud Pierrel, Nicolas Borrel, Thierry Soude
-
Publication number: 20200371541Abstract: An electronic device includes a starting circuit configured to compare a value representative of the power supply voltage with a threshold, wherein the circuit includes a generator of a current proportional to temperature.Type: ApplicationFiled: May 13, 2020Publication date: November 26, 2020Inventors: Jimmy Fort, Maud Pierrel, Nicolas Borrel, Thierry Soude
-
Patent number: 10770411Abstract: A method of protecting a first chip in a multi-chip stack includes determining an electrical characteristic of a conductive loop. The conductive loop extends over a top portion of the first chip. The conductive loop also extends through the first chip and within a top portion of a second chip. The top portion of the second chip is adjacent to a bottom portion of the first chip. The method further includes determining whether the electrical characteristic indicates that an attack is being made to determine contents or operation of the first chip.Type: GrantFiled: April 12, 2019Date of Patent: September 8, 2020Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Clement Champeix, Nicolas Borrel
-
Patent number: 10768229Abstract: A circuit for detecting a glitch in power supply includes a detection circuit to detect the glitch in a DC supply voltage of the power supply when a magnitude in the glitch in a DC supply voltage of the power supply exceeds a detection threshold, wherein the detection threshold is a function of the DC supply voltage, and wherein the detection circuit comprises a low pass filter, a control circuit coupled to the low pass filter, and a current mirror circuit coupled to the control circuit having an output for providing a logic signal indicative of a detected glitch.Type: GrantFiled: August 9, 2018Date of Patent: September 8, 2020Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Nicolas Borrel, Jimmy Fort
-
Patent number: 10691840Abstract: A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.Type: GrantFiled: April 25, 2016Date of Patent: June 23, 2020Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Alexandre Sarafianos, Jimmy Fort, Clement Champeix, Jean-Max Dutertre, Nicolas Borrel
-
Patent number: 10673431Abstract: A power supply voltage is monitored by a monitoring circuit including a variable current generator and a band gap voltage generator core receiving the variable current and including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the variable current generator generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.Type: GrantFiled: October 16, 2018Date of Patent: June 2, 2020Assignee: STMicroelectronics (Rousset) SASInventors: Jimmy Fort, Nicolas Borrel, Francesco La Rosa
-
Patent number: 10560089Abstract: A power supply voltage is monitored by a monitoring circuit including a band gap voltage generator core including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the band gap voltage generator core generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.Type: GrantFiled: October 16, 2018Date of Patent: February 11, 2020Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Borrel, Jimmy Fort, Francesco La Rosa
-
Patent number: 10388724Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.Type: GrantFiled: October 16, 2018Date of Patent: August 20, 2019Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Clement Champeix, Nicolas Borrel, Alexandre Sarafianos
-
Publication number: 20190237415Abstract: A method of protecting a first chip in a multi-chip stack includes determining an electrical characteristic of a conductive loop. The conductive loop extends over a top portion of the first chip. The conductive loop also extends through the first chip and within a top portion of a second chip. The top portion of the second chip is adjacent to a bottom portion of the first chip. The method further includes determining whether the electrical characteristic indicates that an attack is being made to determine contents or operation of the first chip.Type: ApplicationFiled: April 12, 2019Publication date: August 1, 2019Inventors: Clement Champeix, Nicolas Borrel
-
Patent number: 10347595Abstract: A device includes a first chip having a front side and a back side. A second chip is stacked with the first chip and located on the back side of the first chip. A first loop includes first and second through vias located in the first chip. Each through via has a first end on the front side of the first chip and a second end on the back side of the first chip. The first loop also includes a first track that connects the first ends of the first and second through vias is located in the first chip on the front side thereof and a second track that connects the second ends of the first and second through vias is located in the second chip. A detection circuit can detect an electrical characteristic of the first loop.Type: GrantFiled: May 31, 2017Date of Patent: July 9, 2019Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Clement Champeix, Nicolas Borrel