Abstract: Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.

Abstract: In a plasma processing system, a method for dynamically establishing a baseline is provided. The method includes processing a first substrate. The method also includes collecting a first signal data for the first substrate. The method further includes comparing the first signal data against the baseline. The method moreover includes including the first signal data in a recalculation of the baseline if the first signal data is within a confidence level range, which is in between a top level above the baseline and a bottom level below the baseline.

Abstract: A method for affecting a creation of a recipe for processing a substrate in a processing system. The method includes providing a best-known method driven recipe editor. The best-known method driven recipe editor incorporates best-known methods (BKMs), which are best practice specifications for the recipe. The method also includes creating a plurality of BKM modules based on the BKMs for the recipe. The method further includes defining rules for parameters in the plurality of BKM modules. The rules are propagated by the BKMs. The methods moreover includes creating a BKM driven recipe by employing the best-known method driven recipe editor to enter values for the parameters within the guidelines of BKM rules.

Abstract: Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.

Abstract: An apparatus comprising computer readable media is provided. The computer readable media comprises computer readable code for receiving a feature layout and computer readable code for applying shrink correction on the feature layout. The computer readable code for applying the shrink correction comprises providing corner cutouts, adjusting line width and length, shape modifications, etc. for forming features in a patterned layer.

Abstract: Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.

Abstract: A method for generating a plurality of reticle layouts is provided. A feature layout with a feature layout pitch is received. A plurality of reticle layouts is generated from the feature layout where each reticle layout of the plurality of reticle layouts has a reticle layout pitch and where each reticle layout pitch is at least twice the feature layout pitch.

Abstract: A method for affecting a creation of a recipe for processing a substrate in a processing system is provided. The method includes providing a best-know method driven recipe editor. The best-known method driven recipe editor incorporates best-known methods (BKMs), which are best practice specifications for the recipe. The method also includes creating a plurality of BKM modules based on the BKMs for the recipe. The method further includes defining rules for parameters in the plurality of BKM modules. The rules are propagated by the BKMs. The methods moreover includes creating a BKM driven recipe by employing the best-known method driven recipe editor to enter values for the parameters within the guidelines of BKM rules.

Abstract: Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.

Abstract: In a plasma processing system, a method for dynamically establishing a baseline is provided. The method includes processing a first substrate. The method also includes collecting a first signal data for the first substrate. The method further includes comparing the first signal data against the baseline. The method moreover includes including the first signal data in a recalculation of the baseline if the first signal data is within a confidence level range, which is in between a top level above the baseline and a bottom level below the baseline.

Abstract: A method of component management in a substrate processing system is disclosed. The substrate processing system has a set of components, at least a plurality of components of the set of components being designated to be smart components, each component of the plurality of components having an intelligent component enhancement (ICE). The method includes querying the plurality of components to request their respective unique identification data from their respective ICEs. The method further includes receiving unique identification data from the plurality of components if any of the plurality of components responds to the querying. The method additionally includes flagging the first component for corrective action if a first component of the plurality of components fails to provide first component unique identification data when the first component identification data is expected.

Abstract: A method of component management in a substrate processing system is disclosed. The substrate processing system has a set of components, at least a plurality of components of the set of components being designated to be smart components, each component of the plurality of components having an intelligent component enhancement (ICE). The method includes querying the plurality of components to request their respective unique identification data from their respective ICEs. The method further includes receiving unique identification data from the plurality of components if any of the plurality of components responds to the querying. The method additionally includes flagging the first component for corrective action if a first component of the plurality of components fails to provide first component unique identification data when the first component identification data is expected.

Abstract: A method of component management in a substrate processing system is disclosed. The substrate processing system has a set of components, at least a plurality of components of the set of components being designated to be smart components, each component of the plurality of components having an intelligent component enhancement (ICE). The method includes querying the plurality of components to request their respective unique identification data from their respective ICEs. The method further includes receiving unique identification data from the plurality of components if any of the plurality of components responds to the querying. The method additionally includes flagging the first component for corrective action if a first component of the plurality of components fails to provide first component unique identification data when the first component identification data is expected.

Abstract: An apparatus comprising computer readable media is provided. The computer readable media comprises computer readable code for receiving a feature layout and computer readable code for applying shrink correction on the feature layout. The computer readable code for applying the shrink correction comprises providing corner cutouts, adjusting line width and length, shape modifications, etc. for forming features in a patterned layer.

Abstract: A method for generating a plurality of reticle layouts is provided. A feature layout with a feature layout pitch is received. A plurality of reticle layouts is generated from the feature layout where each reticle layout of the plurality of reticle layouts has a reticle layout pitch and where each reticle layout pitch is at least twice the feature layout pitch.

Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry. The etching is timed to etch through a partial thickness of the low dielectric constant layer and the first etch chemistry is optimized to a selected low dielectric constant material. The method further includes forming a via hole in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In a specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

Abstract: Apparatus controls the temperature of a wafer for chemical mechanical polishing operations. A wafer carrier wafer mounting surface positions a wafer adjacent to a thermal energy transfer unit for transferring energy relative to the wafer. A thermal energy detector oriented adjacent to the wafer mounting surface detects the temperature of the wafer. A controller is responsive to the detector for controlling the supply of thermal energy relative to the thermal energy transfer unit. Embodiments include defining separate areas of the wafer, providing separate sections of the thermal energy transfer unit for each separate area, and separately detecting the temperature of each separate area to separately control the supply of thermal energy relative to the thermal energy transfer unit associated with the separate area.

Abstract: A method of component management in a substrate processing system is disclosed. The substrate processing system has a set of components, at least a plurality of components of the set of components being designated to be smart components, each component of the plurality of components having an intelligent component enhancement (ICE). The method includes querying the plurality of components to request their respective unique identification data from their respective ICEs. The method further includes receiving unique identification data from the plurality of components if any of the plurality of components responds to the querying. The method additionally includes flagging the first component for corrective action if a first component of the plurality of components fails to provide first component unique identification data when the first component identification data is expected.

Abstract: Apparatus controls the temperature of a wafer for chemical mechanical polishing operations. A wafer carrier wafer mounting surface positions a wafer adjacent to a thermal energy transfer unit for transferring energy relative to the wafer. A thermal energy detector oriented adjacent to the wafer mounting surface detects the temperature of the wafer. A controller is responsive to the detector for controlling the supply of thermal energy relative to the thermal energy transfer unit. Embodiments include defining separate areas of the wafer, providing separate sections of the thermal energy transfer unit for each separate area, and separately detecting the temperature of each separate area to separately control the supply of thermal energy relative to the thermal energy transfer unit associated with the separate area.

Abstract: A system and method of measuring a metallic layer on a substrate within a multi-step substrate process includes modifying a metallic layer on the substrate such as forming a metallic layer or removing at least a portion of the metallic layer. At least one sensor is positioned a predetermined distance from the surface of the substrate. The surface of the substrate is mapped to determine a uniformity of the metallic layer on the surface of the substrate.