Abstract: The invention includes a drive control integrated circuit with an intelligent and efficient tracing capability. The drive control integrated circuit executes operating instructions grouped into modules. The drive control integrated circuit stores the module numbers for executed modules in a memory. System designers can then retrieve the module numbers from the memory to assess the operation of the drive control integrated circuit. Some typical modules are read, write, seek, error, and servo modules. The drive control integrated circuit also stores operating parameters associated with the executed modules in the memory. Some typical operating parameters are instruction codes, head numbers, cylinder numbers, and error codes. The invention allows system designers to specify a particular trace operation and wait for the drive control integrated circuit to load the module numbers and operational parameters of interest into the memory.

Abstract: The invention includes a method and integrated circuit for testing a disk drive. The invention internally generates test inputs to the host interface in the disk drive. The test inputs emulate the actual inputs that a host computer would provide to the host interface. One version of the invention includes a drive control integrated circuit. The drive control integrated circuit comprises: a host interface, a processor, a buffer control, and compare circuitry. The processor processes test instructions to initiate a test pointer. The buffer control transfers commands from a buffer to the host interface in response to the pointer. The processor controls a write operation and a read operation in response to the commands. The compare circuitry compares the data block that is written to the address with another data block that is read from the address. The compare circuitry generates an alarm if the data blocks do not match.

Abstract: A method of testing a processor controlled chip having embedded circuitry devoid of a direct connection external to said chip. Tracing circuitry embedded on the chip is programmed to detect the presence of specified information on a bus system embedded on the chip and devoid of a direct connection external to the chip. An address comparator detects the presence of the specified information on the bus system and opens gating circuitry in response to the detection. The specified information is extended through the gating circuitry and written in a buffer memory. The specified information can be read out of the buffer memory and extended to a user terminal external to the chip.

Abstract: A write synchronization system in a headerless format magnetic disk device. The system transmits encoded synchronization signals containing disk administration information such as servo burst information between a servo controller and other disk controller components such as a hard disk controller and a microprocessor or digital signal processor. The servo controller interprets the disk administration information read from the magnetic disk and sends an encoded signal to the other disk controller components for each servo burst encountered on when reading the disk. The disk administration information in the signals can be verified by comparing the contents of a present signal to the contents of at least one previous signal to determine if a servo burst from a sequence of servo bursts has been missed. A missing servo burst can also be identified by measuring the time interval between signals from the servo controller.

Abstract: A disk resident system for managing defective data sector information in a defective data sector map in a headerless format magnetic disk device. The defective data sector map is stored in gaps between fields in the headerless disk format itself or in existing disk administration fields. The defective data sector map includes a plurality of binary digits that individually correspond to a defective or non-defective status of an individual data sector on at least one section of at least one track proximate to the defective data sector map. The defective data sector map can be minimized by compressing repetitive 0's or 1's in the map. ECC coding and/or other redundancy checks can be included to ensure validity of the defective data sector map.

Abstract: A disk resident system for managing split data sector information in a headerless format magnetic disk device. The split data sector information is stored in a split data sector information field that is recorded in available areas within a headerless disk format such as the gaps within the headerless disk format or in available space within disk administration fields. Preferred areas within a headerless disk format include the gap immediate preceding a servo burst, the gap immediately following a servo burst, or within the servo burst itself, so that the split data sector information is readily available at the time the servo burst is read and interpreted.

Abstract: A single integrated circuit includes an on-board processor, a peripheral port, and a general purpose input/output (I/O) circuit that support both master mode and slave mode operations. In a master mode of operation, the integrated circuit functions as a disk drive microcontroller and seamlessly interfaces with a hard disk controller. The integrated circuit includes programmable circuitry for generating individual chip select signals for external random access memory (RAM) and external read-only memory (ROM); a fully programmable general purpose input/output interface; and a programmable bi-directional peripheral port. Each of these features are utilized in the master mode to control operation of the disk drive. In a slave mode of operation, the integrated circuit provides full motion control of the spin and tracking systems of a disk drive. In slave mode, the peripheral port is an interface to a host microcontroller or a host RISC processor, that is typically contained within the disk drive.

Abstract: A programmable timing mark sequencer automatically analyzes a sequence of data bits on a data input line. If the appropriate timing pattern is detected in the sequence of data bits, the timing mark sequencer drives a signal active on a servo timing mark output line. The timing mark sequencer is a fully programmable sequencer that is optimized for the detection of servo sector timing mark patterns. The timing mark sequencer includes a branch and fetch unit, a timing mark sequencer random access memory(RAM), an instruction register, a space counter, a window counter, and a synchronization flip-flop. The timing mark sequencer has a plurality of input lines including a search input line, a high resolution data bit line, and a decode clock line.

Abstract: A disk drive controller integrated circuit includes a programmable servo burst decoder that can process any one of a plurality of servo sectors. A disk drive head reads each embedded servo sector on the disk and provides an analog signal, a servo burst, representing the servo sector to a preamp. The preamp provides an amplified analog signal to a read channel integrated circuit. The read channel integrated circuit provides input signals that are processed by the programmable servo burst decoder. The programmable servo burst decoder includes a programmable timing mark sequencer having an instruction register of a first size and a servo timing mark output line, and a programmable burst sequencer connected to the servo timing mark output line and having an instruction register of a second size. In this embodiment, the first size is different from the second size. Specifically, the first size is 20 bits, and the second size is 38 bits.

Abstract: An address mark whose pattern is distinguishable from information data is produced by generating a number of relatively long pulses followed by a number of relatively shorter pulses. Preferably, a binary "1" is recirculated through a first predetermined number of stages of a shift register (for a first pre-established number of times) and then through a second (different) predetermined number of stages (for a second pre-established number of times). A signal level transition which defines the beginning or end of a pulse in the address mark pattern is generated in response to each binary "1" output from that shift register. The address mark pattern is detected by, preferably, supplying an input signal to be detected to the same aforementioned shift register, detecting n successive longer pulses and then detecting m successive shorter pulses, where n and m are less than the aforementioned first and second pre-established numbers, respectively.