Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex machine learning compute operation.

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.

Abstract: An apparatus to facilitate compute optimization is disclosed.

Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Abstract: An apparatus to facilitate compute optimization is disclosed.

Abstract: An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including an input value and a quantized weight value associated with a neural network and an arithmetic logic unit including a barrel shifter, an adder, and an accumulator register, wherein to execute the decoded instruction, the barrel shifter is to shift the input value by the quantized weight value to generate a shifted input value and the adder is to add the shifted input value to a value stored in the accumulator register and update the value stored in the accumulator register.

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

Abstract: An apparatus to facilitate processing of a sparse matrix is disclosed. The apparatus includes a plurality of processing units each comprising one or more processing elements, including logic to read operands, a multiplication unit to multiply two or more operands and a scheduler to identify operands having a zero value and prevent scheduling of the operands having the zero value at the multiplication unit.

Abstract: A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.

Abstract: An apparatus is described having a functional unit of an instruction execution pipeline. The functional unit has a plurality of compare-and-exchange circuits coupled to network circuitry to implement a vector sorting tree for a vector sorting instruction. Each of the compare-and-exchange circuits has a respective comparison circuit that compares a pair of inputs. Each of the compare-and-exchange circuits have a same sided first output for presenting a higher of the two inputs and a same sided second output for presenting a lower of the two inputs, said comparison circuit to also support said functional unit's execution of a prefix min and/or prefix add instruction.

Abstract: Techniques and architecture are disclosed for managing power use during operation of an electronic device capable of processing and/or playback of audio and/or video (AV) content. In some instances, the disclosed techniques/architecture can be used, for example: (1) to stop decoding and/or rendering of AV content upon detecting that a user wishes to stop or is otherwise unable to consume (e.g., hear/listen to or otherwise utilize) such AV content; and/or (2) to continue/re-enable decoding and/or rendering of AV content upon detecting that a user wishes or is otherwise able to continue/resume consumption thereof. In some cases, use of the disclosed techniques/architecture may reduce central processing unit (CPU) cycles, audio digital signal processing (DSP), rendering hardware usage, etc., and/or otherwise make more efficient use of battery charge, and thus may realize an improvement in battery life, for example, for a mobile/battery-operated device capable of AV processing and/or playback.

Abstract: An apparatus is described having a functional unit of an instruction execution pipeline. The functional unit has a plurality of compare-and-exchange circuits coupled to network circuitry to implement a vector sorting tree for a vector sorting instruction. Each of the compare-and-exchange circuits has a respective comparison circuit that compares a pair of inputs. Each of the compare-and-exchange circuits have a same sided first output for presenting a higher of the two inputs and a same sided second output for presenting a lower of the two inputs, said comparison circuit to also support said functional unit's execution of a prefix min and/or prefix add instruction.

Abstract: Techniques and architecture are disclosed for managing power use during operation of an electronic device capable of processing and/or playback of audio and/or video (AV) content. In some instances, the disclosed techniques/architecture can be used, for example: (1) to stop decoding and/or rendering of AV content upon detecting that a user wishes to stop or is otherwise unable to consume (e.g., hear/listen to or otherwise utilize) such AV content; and/or (2) to continue/re-enable decoding and/or rendering of AV content upon detecting that a user wishes or is otherwise able to continue/resume consumption thereof. In some cases, use of the disclosed techniques/architecture may reduce central processing unit (CPU) cycles, audio digital signal processing (DSP), rendering hardware usage, etc., and/or otherwise make more efficient use of battery charge, and thus may realize an improvement in battery life, for example, for a mobile/battery-operated device capable of AV processing and/or playback.

Abstract: Techniques and architecture are disclosed for managing power use during operation of an electronic device capable of processing and/or playback of audio and/or video (AV) content. In some instances, the disclosed techniques/architecture can be used, for example: (1) to stop decoding and/or rendering of AV content upon detecting that a user wishes to stop or is otherwise unable to consume (e.g., hear/listen to or otherwise utilize) such AV content; and/or (2) to continue/re-enable decoding and/or rendering of AV content upon detecting that a user wishes or is otherwise able to continue/resume consumption thereof. In some cases, use of the disclosed techniques/architecture may reduce central processing unit (CPU) cycles, audio digital signal processing (DSP), rendering hardware usage, etc., and/or otherwise make more efficient use of battery charge, and thus may realize an improvement in battery life, for example, for a mobile/battery-operated device capable of AV processing and/or playback.

Abstract: Techniques and architecture are disclosed for managing power use during operation of an electronic device capable of processing and/or playback of audio and/or video (AV) content. In some instances, the disclosed techniques/architecture can be used, for example: (1) to stop decoding and/or rendering of AV content upon detecting that a user wishes to stop or is otherwise unable to consume (e.g., hear/listen to or otherwise utilize) such AV content; and/or (2) to continue/re-enable decoding and/or rendering of AV content upon detecting that a user wishes or is otherwise able to continue/resume consumption thereof. In some cases, use of the disclosed techniques/architecture may reduce central processing unit (CPU) cycles, audio digital signal processing (DSP), rendering hardware usage, etc., and/or otherwise make more efficient use of battery charge, and thus may realize an improvement in battery life, for example, for a mobile/battery-operated device capable of AV processing and/or playback.