Abstract: A system for displaying critical and non-critical information on a screen includes, in the same housing, at least one electronic computing circuit and an electronic monitoring circuit. The electronic computing circuit is programmed to process the critical information to be displayed, construct at least one image from non-critical information and incorporate therein the critical information to be displayed in order to form, on an output of the electronic computing circuit, an image signal intended to be transmitted to the screen. The electronic monitoring circuit has an input connected to said output and is programmed to determine expected critical information for the display and to verify whether the image signal contains information corresponding to the expected critical information. Aircraft equipped with such a system.

Abstract: An on-board computer includes a microprocessor chip with a lower face and an upper face, a chip carrier having an upper face on which the microprocessor chip is mounted, and a casing configured to discharge heat generated by the microprocessor chip in operation. An interposer is disposed between the upper face and the casing. The interposer diffuses the heat transmitted by the upper face of the microprocessor chip towards the casing. The interposer has an upper surface for heat exchange with the casing that is twice or more greater than the surface area of the upper face of the microprocessor chip. The interposer has on one or more sides a peripheral wedging rim coming into contact with a side wall of the chip carrier, and has no more than two peripheral wedging rims, in order to leave the other sides of the interposer free.

Abstract: The invention relates to: Control circuit (1) for an electrical device (2), said control circuit (1) receiving as input a discrete electrical control signal (CMD), the control circuit (1) comprising a source (11) of voltage (±V) configured so as to supply the circuit according to a negative or positive voltage; a switch (12) normally closed in the absence of any discrete electrical control signal (CMD) and configured so as to isolate the electrical device from the voltage source as a function of the electrical control signal (CMD), said switch being connected between the voltage source and the electrical device (2); the switch (12) being sensitive to the discrete electrical control signal (CMD) for just one sense of voltage.

Abstract: The invention concerns a system on a chip (100) comprising a set of master modules which includes a main processing module (101a) and a direct memory access controller (DMA) (102a) associated with said module (101a), and at least one secondary processing module (101b) and a DMA (102b) associated with said module (101b), and slave modules; each master module being configured for connection to a clock source, a power supply, and slave modules which include a set of proximity peripherals (105a,b), at least one internal memory (104a,b) and a set (106) of peripherals and external memories shared by the master modules; said clock source, power supply, proximity peripherals (105a,b) and a cache memory (103a,b) of a master processing module and its DMA being dedicated to said master processing module and not shared with the other processing modules of the set of master modules; and said at least one internal memory (104a,b) of each master processing module and its DMA being dedicated to said master processing module,

Abstract: The invention relates to: Control circuit (1) for an electrical device (2), said control circuit (1) receiving as input a discrete electrical control signal (CMD), the control circuit (1) comprising a source (11) of voltage (±V) configured so as to supply the circuit according to a negative or positive voltage; a switch (12) normally closed in the absence of any discrete electrical control signal (CMD) and configured so as to isolate the electrical device from the voltage source as a function of the electrical control signal (CMD), said switch being connected between the voltage source and the electrical device (2); the switch (12) being sensitive to the discrete electrical control signal (CMD) for just one sense of voltage.

Abstract: The invention concerns a bandwidth control method in an on-chip system comprising at least one main master module, at least one secondary master module, at least one slave module and a bus connected to each module on a communication link, the bus comprising interconnection means to make at least one common slave module communicate with at least one main master module and with at least one secondary master module via at least one common path portion, the method comprising the following steps carried out for each common slave module: first detection of a first request to access the common slave module, issued by a main master module, definition of a blocking time Dj associated with the common slave module, blocking, during blocking time Dj, of any data transfer on the at least one common path portion between a secondary master module and the common slave module.

Abstract: The invention in particular concerns a method for filtering access to an on-chip system comprising at least one master module, at least one slave module and a bus, the bus comprising at least one slave port, at least one master port and means for interconnection between at least one of the slave ports and at least one of the master ports, the method being characterised in that it comprises the following steps implemented when an access request is routed from a master module connected to a slave port to a slave module connected to a master port: intercepting an item of source information on the link between the master port and the slave module before the slave module receives the request, searching for the item of source information in at least one access control list controlling access to the slave module, blocking the request such that the slave module is unaware of the requested access if the item of source information is not found in the at least one access control list.

Abstract: The invention concerns a method for monitoring transactions in an on-chip system comprising at least one main master module, at least one secondary master module, at least one slave module and a bus connected to each module, the bus comprising interconnection means to make at least one common slave module communicate with at least one main master module and with at least one secondary master module, the method comprising the following steps implemented during each transaction between a secondary master module and a common slave module: starting a counter upon initial detection of a transaction start signal, waiting for a final detection of a transaction end signal within a predefined time T, closing the transaction if the time tc that has elapsed since starting the counter is greater than predefined time Tmax, and reinitialising the counter.

Abstract: The present invention relates to a device making it possible to manage a flash memory component designed for onboard computers notably in the aviation field. In particular, the invention makes it possible to use NAND flash memory media in fields such as aviation, by virtue of its judicious organisation and management of the flash memory components. On the one hand it makes it possible to optimise and on the other hand to control the lifetime of the flash memories.